Fuse Memory Access Control via Finite State Machine

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Solution Overview

Problem

Integrated circuits with irreversibly-programmable non-volatile memories face challenges in securely allowing access for testing while protecting sensitive information, as existing methods like JTAG interfaces can compromise confidential data during defect analysis.

Innovation Solution

A finite state machine controls the access to fuse-type non-volatile memory, conditioning the circuit between 'open' and 'closed' states based on fuse word values, allowing secure testing without exposing sensitive data by limiting access to the processor and enabling scan tests only when authorized.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the JTAG interface is used to allow access for testing the integrated circuit, then the ability to perform defect analysis is improved, but the security of sensitive information stored in the fuse memory is compromised

Engineering Contradiction:
Improvetesting accessVSAvoiddata exposure risk
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The fuse memory is divided into multiple words, with specific fuse words dedicated to storing security parameters (transition counts) that control access rights. This segmentation allows the system to separate sensitive data from testable data, enabling selective access control during JTAG testing operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The security parameters are pre-stored in the fuse memory during manufacturing before the integrated circuit is deployed. These pre-stored parameters establish the rules for future access control, allowing the system to automatically verify and enforce security policies without requiring external intervention during testing operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the fuse memory content is made accessible for testing, then manufacturing defect analysis is enabled, but confidential data such as authentication keys and cipher keys are exposed

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidconfidential data exposure
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

A security verification mechanism acts as an intermediary between the JTAG interface and the fuse memory content. This intermediary verifies security parameters stored in dedicated fuse words before allowing access to memory contents, thereby preventing direct exposure of confidential data while still enabling defect analysis through controlled access.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Different regions of the fuse memory have different access properties. Certain fuse words contain security-critical data with restricted access, while other areas contain testable data with more permissive access rights. This local differentiation of access quality allows simultaneous defect analysis and security protection.

Inventive Principle:
Principle #3Local quality

3Object-affected harmful factors

If the circuit is kept in a closed state to protect secret information, then data security is maintained, but the ability to perform scan tests is lost

Engineering Contradiction:
Improveinformation securityVSAvoidtesting efficiency
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The circuit's access state is made dynamic rather than static. The system can transition between closed and open states based on verification of security parameters. This dynamic behavior allows the circuit to maintain security by default while enabling testing operations when security conditions are satisfied, thereby resolving the contradiction between security and testing efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The security state of the circuit is determined by parameters stored in the fuse memory (transition counts). By changing these parameters or their interpretation, the system can switch between secure closed states and permissive open states, allowing flexible control over the balance between security and testing productivity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250004051A1Protection of the content of a fuse memory
Publication Date: 2025.01.02 STMICROELECTRONICS (GRENOBLE 2) SAS
  • US20250004051A1 patent drawing
  • US20250004051A1 patent drawing
  • US20250004051A1 patent drawing

AI summary

The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.