Fuse Memory Cell Array with Bilateral Symmetry
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Solution Overview
Problem
Existing non-volatile memory devices with fuse-type cell arrays face challenges in minimizing the area occupied by each unit cell due to the inclusion of MOS transistors, which increases the overall size of the memory device.
Innovation Solution
The proposed solution involves a non-volatile memory device with a fuse-type cell array that includes a discharge circuit for a common node for each column, allowing for a bilaterally symmetrical structure of unit cells connected through a common node, and the use of a p-type guard ring to minimize leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a MOS transistor is included in each unit cell to enable fuse blowing operation, then the fuse can be properly programmed, but the area of each unit cell increases
Solution Approach 1:
The patent merges the word line and bit line into a single bit line that serves dual purposes: it acts as both the word line for selecting unit cells and the bit line for reading data. This merging eliminates the need for separate word lines in each unit cell, thereby reducing the area occupied by each unit cell while maintaining the ability to properly program fuses through the shared bit line structure
Solution Approach 2:
The bit line is designed to perform multiple functions simultaneously: it serves as the word line for cell selection during programming operations and as the bit line for data reading operations. This multi-functionality reduces the overall wiring complexity and area requirements compared to having dedicated separate lines for each function
2Area of stationary object
If the unit cell area is reduced to minimize overall device size, then the memory device becomes more compact, but leakage current between adjacent unit cells increases
Solution Approach 1:
The patent introduces guard rings with specific doping concentrations positioned between adjacent unit cells. These guard rings have different electrical properties (higher doping concentration) compared to the surrounding regions, creating localized potential barriers that confine leakage current within specific regions and prevent it from spreading to adjacent unit cells, thus addressing the leakage issue in the context of reduced unit cell area
3Productivity
If voltage is applied to program a fuse in one unit cell, then the fuse can be blown, but voltage discharge may damage fuses in other unit cells
Solution Approach 1:
The guard rings act as intermediary structures positioned between adjacent unit cells. During fuse programming operations, these guard rings serve as voltage barriers that contain the high voltage applied to a specific unit cell within its boundaries, preventing the voltage from discharging into adjacent unit cells and damaging their fuses, while still allowing efficient programming of the target cell
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes the area occupied by the fuse-type cell array, reduces leakage current, and prevents damage to fuses in other unit cells due to voltage discharge during program operations.
Implementation Method 1
a PN diode, a first NMOS transistor, and a fuse, wherein a first type unit cell and a second type unit cell may be connected to each other through a common node
Implementation Method 2
A p-type guard ring disposed to surround the first type unit cell and the second type unit cell may be further included
Data Source
AI summary
A memory device includes an eFuse cell array in which unit cells of different types are alternately disposed, and each of the unit cells of different types includes a PN diode, a first NMOS transistor, and a fuse, wherein a first type unit cell and a second type unit cell are connected to each other through a common node, and the first type unit cell and the second type unit cell are disposed in a bilaterally symmetrical structure with respect to the common node.