Fuse Memory Circuit with Shared Programming and Diode Isolation
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Solution Overview
Problem
As memory cells become smaller and more complex, the resistance of conductive lines within these devices are affected, impacting their performance, and existing non-volatile memory technologies face challenges in efficiently storing data while minimizing circuit area.
Innovation Solution
A memory circuit design that incorporates fuse elements configured in high or low resistance states for data storage, shared programming devices to reduce area, and diodes to prevent unintended current paths, thereby improving performance and reducing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are made smaller and more complex, then storage capacity increases, but resistance of conductive lines changes affecting performance
Solution Approach 1:
The patent transitions from planar 2D memory cell layouts to vertically stacked 3D structures, stacking multiple memory cell layers above a common substrate. This dimensional change increases storage capacity without proportionally increasing footprint area, and the vertical architecture provides better control over conductive line resistance through shortened current paths and improved material utilization.
2Duration of action of stationary object
If non-volatile memory technologies are used for data storage, then data retention is improved, but circuit area increases
Solution Approach 1:
The patent merges multiple memory cell layers into a single vertical stack sharing common bit lines and word line structures. This consolidation provides non-volatile data retention across multiple layers while reducing the overall circuit footprint by eliminating redundant conductive lines that would otherwise be required for separate memory cells.
Solution Approach 2:
The stacked memory architecture uses shared bit lines and control circuits that serve multiple memory cell layers simultaneously. This multi-functionality enables non-volatile storage across several layers while using a single set of read/write circuitry, thereby reducing the total circuit area compared to implementing separate non-volatile memory cells for each layer.
3Area of stationary object
If programming devices are shared among multiple fuse elements, then area is reduced, but device complexity increases
Solution Approach 1:
The patent segments the programming operation into controlled phases using selection devices that activate specific fuse elements or groups. Each programming device is paired with selection transistors that segment the programming current paths, allowing multiple fuse elements to share programming devices while maintaining simple individual programming operations through selective activation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively stores data in a non-volatile manner while significantly reducing the memory circuit's overall area by up to 40% and enhances performance by preventing unintended current paths.
Implementation Method 1
fuse elements configured as non-volatile memory and configured in a high resistance state or a low resistance state
Implementation Method 2
a diode connected in series with the fourth fuse element, wherein the diode blocks a current flow through the fourth fuse element
Data Source
AI summary
A method of operating a memory circuit includes turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element. The first fuse element is coupled between the first selection device and the first programming device. The method further includes turning off a second programming device and turning off a second selection device, and blocking the first current from flowing through a second fuse element that is coupled between the second selection device and the first programming device.