Fuse-Programmed Pulse Width Control for Process-Compensated Delay Cells
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Solution Overview
Problem
Conventional pulse control devices in DRAMs generate pulses with varying widths due to changes in process conditions and temperature, leading to operational inconsistencies and errors in data transmission.
Innovation Solution
A pulse control device with a fuse set and mode register that selectively adjusts the number of delay cells based on programmed information to maintain a constant pulse width, using delay increase and decrease signals to compensate for process and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pulse control devices use fixed delay cells to generate internal pulses, then the circuit structure is simple, but the pulse width varies with process and temperature changes causing operational errors
Solution Approach 1:
The patent implements dynamic adjustment of delay cell quantity through fuse set and mode register set configurations. The delay cell array can be selectively enabled or disabled based on process conditions and temperature, allowing the pulse width to be dynamically optimized for different operating environments rather than being fixed.
Solution Approach 2:
The patent changes the parameter of delay cell quantity to compensate for process and temperature variations. By adjusting how many delay cells are activated in the array, the system maintains consistent pulse width despite external condition changes, directly addressing the reliability issue.
2Manufacturing precision
If the number of delay cells is increased to compensate for process variations, then pulse width stability improves, but the device complexity and area increase
Solution Approach 1:
The patent segments the delay cells into multiple groups that can be independently controlled. Instead of using a single large delay element, the delay functionality is divided into smaller units that can be selectively activated. This segmentation allows precise adjustment of total delay with minimal circuit area, as only the necessary number of delay cells are enabled based on process conditions.
Solution Approach 2:
The system dynamically adjusts the number of active delay cells based on fuse set configurations and mode register settings. This dynamic capability allows the circuit to achieve precise pulse width control without permanently allocating maximum delay resources, thereby reducing overall circuit area while maintaining manufacturing precision.
3Adaptability or versatility
If multiple delay cell configurations are provided for different processes, then adaptability to process variations improves, but the device complexity increases
Solution Approach 1:
The patent implements preliminary configuration through fuse sets that are programmed during manufacturing to match specific process conditions. The fuse configurations pre-establish the appropriate delay cell activation patterns for different process variations, eliminating the need for complex real-time decision logic. This preliminary action simplifies the control structure while maintaining high adaptability.
Solution Approach 2:
The mode register set acts as an intermediary between the fuse configurations and the delay cell array. It translates the fuse settings into appropriate control signals that enable or disable specific delay cells. This intermediary layer simplifies the overall control logic by providing a clear separation between configuration storage and execution, reducing device complexity while maintaining adaptability.
Data Source
AI summary
Provided is a pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.