Integrated Circuit Electrical Fuse Programming Reliability

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Solution Overview

Problem

The scaling down of semiconductor devices to increase functional density and reduce geometry size leads to high power dissipation, which is addressed by using CMOS devices with metallic materials for gates and dielectrics, but these materials pose challenges in programming electrical fuses due to high electron migration reliability.

Innovation Solution

The integration of CMOS devices with gate-last high-K metal gate processes, where metallic materials are used for transistors and semiconductor materials for fuses, with a diffusion barrier to prevent electron migration, allowing for reliable programming by differing materials for transistors and fuses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If metallic materials are used for transistor gates to reduce power dissipation, then power consumption is reduced, but programming electrical fuses becomes difficult due to high electron migration reliability

Engineering Contradiction:
Improvepower dissipationVSAvoidprogramming reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies different material compositions to different regions: metallic gate materials (e.g., tungsten, titanium nitride) are used for transistor gates to minimize electron migration and reduce power dissipation, while semiconductor materials (e.g., polysilicon, silicon-germanium) are used for fuse elements to enable reliable programming. This local differentiation allows each component to have optimal properties for its specific function.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the integrated circuit into distinct functional regions with different material properties: transistor regions use metallic gate structures for low power operation, while fuse regions use semiconductor materials for programmability. This segmentation allows the circuit to simultaneously achieve low power consumption and reliable programming capability.

Inventive Principle:
Principle #1Segmentation

2Productivity

If geometry size is scaled down to increase functional density, then functional density is increased, but power dissipation increases

Engineering Contradiction:
Improvefunctional densityVSAvoidpower dissipation
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent changes the material parameter (from semiconductor to metal) for gate electrodes in scaled-down devices. Metallic gate materials provide higher conductivity and better electrostatic control, enabling continued scaling while managing power dissipation. This parameter change allows functional density to increase without proportional increases in power consumption.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of programming electrical fuses by minimizing electron migration, ensuring effective operation and adaptability in integrated circuits.

Implementation Method 1

a diffusion barrier to prevent electron migration

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

passing an electrical current of a sufficient magnitude to cause melting or agglomeration

Methodology Applied
Scientific EffectMelting: Melting

Implementation Method 3

passing an electrical current of a sufficient magnitude to cause melting

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS9524934B2Integrated circuits with electrical fuses and methods of forming the same
Publication Date: 2016.12.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9524934B2 patent drawing
  • US9524934B2 patent drawing
  • US9524934B2 patent drawing

AI summary

A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.