Fuse Protection Circuit for Semiconductor ESD Management

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Solution Overview

Problem

Semiconductor devices with redundant fuses face challenges in protecting the gate insulating films of internal transistors from electrical static discharge (ESD) during the manufacturing and scribing processes, as the cut sections of the fuses are exposed and prone to electrical charges that can cause breakdown.

Innovation Solution

The implementation of ESD protection circuits that include diodes and resistors connected to the fuses, which discharge electrical charges to the substrate potential, preventing the transfer of ESD surges to the gate terminals of transistors and thus protecting the gate insulating films. These circuits utilize diffusion layers and resistors to efficiently manage and dissipate ESD surges, reducing the risk of breakdown.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the fuse cut section is exposed to the outside for laser cutting and inspection, then the fuse can be effectively cut and tested, but the cut section becomes vulnerable to ESD charges that can break down the gate insulating film of internal transistors

Engineering Contradiction:
Improvefuse cutting precisionVSAvoidgate insulating film integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent introduces a protection circuit as an intermediary component between the exposed fuse cut section and the internal transistor gate terminals. This protection circuit includes a first discharge path with a first capacitor and first resistor connected to the fuse cut section, and a second discharge path with a second capacitor and second resistor connected to the gate terminal. These intermediary elements capture and discharge ESD charges before they can reach and damage the gate insulating film, thus resolving the contradiction between exposing the fuse for manufacturing and protecting the internal circuit.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If ESD protection measures are added to protect the internal circuit from fuse cut section charges, then the gate insulating film is protected, but the device complexity increases

Engineering Contradiction:
Improvegate insulating film integrityVSAvoidprotection circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the ESD protection function into a separate, dedicated protection circuit that is specifically designed to handle charges from the fuse cut section. By taking out this protection function as an independent subsystem with its own discharge paths (first and second discharge paths), capacitors, and resistors, the main internal circuit remains simple while the extractioned protection circuit handles the ESD protection task, thus protecting the gate insulating film without significantly complicating the overall device.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The ESD protection circuits effectively prevent the breakdown of gate insulating films by discharging electrical charges to the substrate potential, ensuring the reliability and integrity of the semiconductor device even when exposed to ESD surges during the scribing process, thereby enhancing the protection of internal transistors.

Implementation Method 1

The implementation of ESD protection circuits that include diodes and resistors connected to the fuses, which discharge electrical charges to the substrate potential

Methodology Applied
Scientific EffectElectrical charge discharge: Electrostatic Discharge

Data Source

PatentUS7816761B2Semiconductor device having fuse and protection circuit
Publication Date: 2010.10.19 LAPIS SEMICON CO LTD
  • US7816761B2 patent drawing
  • US7816761B2 patent drawing
  • US7816761B2 patent drawing

AI summary

A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.