Fuse Read Latch Circuit for Sub-1V High-Stand-Off MOSFETs
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Solution Overview
Problem
Existing technologies face challenges in reliably reading fusible links using low-voltage logic circuitry, particularly in applications requiring high-voltage stand-off capability for MOSFET devices.
Innovation Solution
The proposed solution involves a latch circuit and a pair of voltage dividers to generate a reference voltage and a testable fuse voltage, allowing for reliable comparison and latching of the greater voltage, all while operating at a supply voltage below 1V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If MOSFETs are fabricated with high-voltage stand-off capability (3.6V process), then voltage withstand capability is improved, but threshold voltage increases to near 0.9V which prevents low-voltage operation (VDD_MIN of about 1V)
Solution Approach 1:
The circuit is divided into two distinct voltage domains: a high-voltage domain for the MOSFET stand-off capability and a low-voltage domain for the logic circuitry operation. The high-voltage MOSFETs provide the necessary voltage withstand capability while the low-voltage logic circuits operate at VDD_MIN of about 1V, allowing each segment to optimize for its specific voltage requirement without compromise
Solution Approach 2:
Voltage level shifting circuits and level translators are introduced as intermediary components between the high-voltage MOSFET domain and the low-voltage logic domain. These intermediaries enable signal transfer and coordination between the two voltage domains, allowing the high-voltage stand-off capability to coexist with low-voltage operation
2Use of energy by moving object
If conventional fuse read circuits are used with low-voltage logic, then power consumption is reduced, but reliable operation becomes difficult due to threshold voltage limitations
Solution Approach 1:
The circuit employs parameter changes by dynamically adjusting voltage levels and current magnitudes during the fuse read operation. Specialized low-voltage comparator circuits are designed with modified parameters (such as higher gain, adjusted reference voltages, and optimized transistor sizing) to ensure reliable operation at VDD_MIN of about 1V, maintaining sufficient noise margins and detection capability despite the reduced supply voltage
3Quantity of substance
If large-scale fuse arrays are implemented, then memory capacity is increased, but circuit area and complexity increase
Solution Approach 1:
Multiple fuse arrays are merged and organized into banks, with shared control and readout circuitry. The patent implements a hierarchical structure where fuses are grouped into arrays, arrays are organized into banks, and banks share common control logic and comparator resources. This merging approach increases memory capacity while minimizing the proportional increase in control circuitry area
Solution Approach 2:
The control and readout circuits are designed with multi-functionality to serve multiple fuse arrays and banks. A single set of control logic, voltage dividers, and comparator circuits can read fuses from different banks by selectively enabling appropriate arrays, reducing the need for dedicated circuitry for each array and thereby minimizing overall circuit area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides predictable operation that is less susceptible to PVT variations, enables the use of large-scale fuse arrays, and does not require additional pins or increased integrated circuit area.
Implementation Method 1
a pair of voltage dividers to generate a reference voltage VREF and a testable fuse voltage VFUSE
Data Source
AI summary
Circuits and methods for reading fusible links that allows use of low-voltage logic circuitry utilizing devices that may have a high-voltage stand-off capability. Embodiments provide predictable operation that is less susceptible to PVT variations, allow the use of arrays of fuses that may be scaled to relatively large memory sizes, uses little integrated circuit area, and do not require extra pins for operation. Embodiments utilize a latch circuit and voltage dividers to generate a reference voltage VREF and a fuse voltage VFUSE, and then compares and latches the greater of those voltages. The circuitry does not require any more supply voltage than is needed to turn ON input pass transistors to the latch at a slightly higher voltage (VTH) than VREF. Since VREF may be about 0.1V, that turn-ON voltage may be as low as about 0.1V+VTH, and thus would be less than a VDD_MIN of about 1V.