Fuse Read Circuit Using Voltage Dividers for Low-Voltage Sensing
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Solution Overview
Problem
Existing methods for reading fusible links in electronic circuits face challenges when using low-voltage logic circuitry with high-voltage stand-off capability, particularly in applications like RF switching, where MOSFETs require specific process characteristics and customer applications operate at low supply voltages, making it difficult to reliably sense fuse states.
Innovation Solution
The solution involves a latch circuit and a pair of voltage dividers to generate a reference voltage and a testable fuse voltage, allowing comparison and latching of the greater voltage, which operates at a supply voltage as low as 1V, utilizing a latch circuit and voltage dividers to generate reference and testable fuse voltages for reliable comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If MOSFETs are designed with high-voltage stand-off capability (3.6V process), then they can withstand high voltages, but their threshold voltage VTH becomes close to low supply voltage (up to 0.9V vs 1V minimum), making fuse reading unreliable
Solution Approach 1:
The circuit segments the voltage comparison function into two independent voltage dividers: one for generating reference voltage (VREF) and another for generating fuse voltage (VFUSE). This segmentation allows each divider to be optimized independently, ensuring reliable operation even when VTH approaches VDD_MIN.
Solution Approach 2:
The invention changes the parameter of supply voltage requirement by designing the voltage dividers and latch circuit to operate reliably at low supply voltages (as low as 1V). The voltage dividers use resistor ratios to generate proportional voltages that remain distinguishable even at low VDD, enabling reliable fuse reading despite the high VTH of high-voltage MOSFETs.
2Ease of operation
If conventional fuse reading circuits are used, then they can read fuse states, but they require more supply voltage than available in low-voltage applications
Solution Approach 1:
The circuit changes the operating voltage parameter by designing voltage dividers with appropriate resistor ratios that generate sufficient voltage differential for reliable latch operation at low supply voltages. The reference voltage VREF is set to approximately 0.1V, allowing the latch to turn ON at voltages as low as 0.1V + VTH, which is below the 1V minimum supply voltage.
Solution Approach 2:
The voltage dividers act as intermediaries that transform the high-voltage MOSFET operation into low-voltage compatible signals. By dividing down the voltages proportionally, the circuit enables fuse state detection without requiring the full high-voltage level, thus bridging the gap between high-voltage device requirements and low-voltage logic operation.
3Reliability
If voltage dividers and latch circuit are used to generate and compare voltages, then fuse reading becomes reliable at low voltage, but circuit complexity increases
Solution Approach 1:
The voltage dividers serve multiple functions: they generate reference voltages, provide voltage scaling, and enable level shifting between high-voltage and low-voltage domains. The latch circuit simultaneously performs voltage comparison and state latching. This multi-functionality reduces the need for additional dedicated circuits, thereby limiting the increase in overall circuit complexity.
Solution Approach 2:
The invention merges the voltage generation, voltage comparison, and state latching functions into a single integrated circuit block. The two voltage dividers and latch circuit work together as a unified fuse reading mechanism, eliminating the need for separate high-voltage and low-voltage circuit domains and reducing overall system complexity.
Data Source
AI summary
Circuits and methods for reading fusible links that allows use of low-voltage logic circuitry utilizing devices that may have a high-voltage stand-off capability. Embodiments provide predictable operation that is less susceptible to PVT variations, allow the use of arrays of fuses that may be scaled to relatively large memory sizes, uses little integrated circuit area, and do not require extra pins for operation. Embodiments utilize a latch circuit and voltage dividers to generate a reference voltage VREF and a fuse voltage VFUSE, and then compares and latches the greater of those voltages. The circuitry does not require any more supply voltage than is needed to turn ON input pass transistors to the latch at a slightly higher voltage (VTH) than VREF. Since VREF may be about 0.1V, that turn-ON voltage may be as low as about 0.1V+VTH, and thus would be less than a VDD_MIN of about 1V.