Fuse Readout Timing Control for Low-Power Reset
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Solution Overview
Problem
In semiconductor devices with a reset terminal, the continuous flow of current through unblown fuse elements during external reset signal activation leads to excessive current consumption, particularly in low-power modes like deep power down, due to the conventional fuse circuit design.
Innovation Solution
A semiconductor device with a timing control circuit that generates internal reset signals in response to the transition of the external reset signal, allowing for controlled reading of nonvolatile memory elements and minimizing current flow through fuse elements, and a latch circuit that is reset based on the activation period of the external reset signal to stabilize output and prevent malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional fuse circuit design is used where the fuse is constantly read out during the activation period of the reset signal, then the latch circuit can be reset and information can be loaded correctly, but current keeps flowing through unblown fuse elements causing excessive current consumption in low-power modes
Solution Approach 1:
The patent applies periodic action by controlling the fuse read-out operation to occur only during a specific time window (from reset signal activation to a predetermined time point before reset signal deactivation). This periodic control ensures that current flows through the fuse element only when necessary for reading, rather than continuously during the entire reset signal activation period, thereby reducing power consumption while maintaining reset reliability
Solution Approach 2:
The patent implements preliminary action by generating the fuse read-out signal in advance based on the reset signal timing. The read-out operation is prepared and executed during the appropriate time window before the reset signal deactivates, ensuring that the latch circuit receives the correct information before the reset operation completes, thus maintaining reliability while controlling current consumption
2Stability of the object's composition
If the external reset signal activation period is lengthened to ensure proper reset operation, then the latch circuit has sufficient time to stabilize, but current consumption through unblown fuse elements increases
Solution Approach 1:
The patent uses periodic action to confine the fuse read-out operation to a specific time window within the reset signal activation period. By controlling the read-out to occur only during this predetermined window and stopping before the reset signal deactivates, the system achieves latch circuit stabilization without extending the overall reset period, thereby minimizing current consumption while ensuring stability
Solution Approach 2:
The timing control circuit automatically manages the fuse read-out timing based on the reset signal characteristics without requiring external intervention. The circuit self-regulates the read-out operation to occur at the appropriate time window, ensuring both latch stability and current consumption control through autonomous timing management
Data Source
AI summary
A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.