DRAM Fuse Structure With Segmented Gate And STI
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Solution Overview
Problem
Current DRAM devices with buried gate structures face limitations in fabrication capability, affecting performance and reliability, particularly in achieving higher integration and density as electronic products miniaturize.
Innovation Solution
The method involves forming a fuse structure with shallow trench isolation (STI) and multiple gate structures, including select and assist gates, on a substrate, utilizing ion implantation and etching processes to create doped regions and conductive layers, allowing for efficient fabrication of DRAM devices with improved performance and reduced voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar gate structures are used in DRAM units, then fabrication is simpler, but carrier channel length is shorter leading to increased capacitor leakage
Solution Approach 1:
The gate structure is segmented into multiple components including select gates, assist gates, and control gates positioned at different locations (substrate, STI region, and overlapping regions). This segmentation allows each gate component to perform specific functions in controlling the fuse structure, achieving better leakage prevention while maintaining fabrication feasibility through modular construction
Solution Approach 2:
The invention transitions from a conventional planar 2D gate structure to a three-dimensional multi-layer gate configuration. Gates are positioned at different vertical and horizontal levels, with some gates on the substrate, others on the STI, and control gates overlapping multiple regions. This dimensional expansion increases the effective carrier channel length without proportionally increasing the planar footprint, thereby reducing capacitor leakage while maintaining area efficiency
2Productivity
If DRAM units are miniaturized for higher integration, then device density increases, but fabrication capability limitations affect performance and reliability
Solution Approach 1:
The gate structure serves multiple functions simultaneously: select gates control access to memory cells, assist gates provide additional control for precise timing, and control gates regulate overall operation. This multi-functionality allows a single integrated structure to perform what would traditionally require multiple separate components, enabling higher density while maintaining reliable fabrication processes
Solution Approach 2:
The gate structure employs a nested configuration where control gates overlap and encompass multiple underlying gate structures (select gates and assist gates). This nesting allows compact arrangement of multiple functional elements within a small area, achieving high integration density while maintaining distinct functional zones that can be reliably fabricated using standard semiconductor processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and reliability of DRAM devices by enabling smaller memory cell sizes and lower voltage operations, improving integration and density, and addressing the limitations of existing buried gate structure fabrication.
Implementation Method 1
utilizing ion implantation and etching processes to create doped regions and conductive layers
Data Source
AI summary
A fuse structure for dynamic random access memory (DRAM) includes: a shallow trench isolation (STI) in a substrate; a first select gate in the substrate and adjacent to one side of the STI; a second select gate in the substrate and adjacent to another side of the STI; and a gate structure on the STI, the first select gate, and the second select gate.