Fuse-Based Sequential Testing for IC Pad Constrained Space
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Solution Overview
Problem
The increasing number of test elements in semiconductor devices necessitates a more efficient testing method due to the limited space available for pads, as each test element is typically connected to a single pad, leading to a need for a method to test multiple elements effectively with a restricted number of pads.
Innovation Solution
The use of fuse elements to sequentially test vertically-integrated test elements, where a first test element is connected to a pad via a fuse, tested, and then the fuse is cut to disconnect it, allowing a second test element to be tested using the same pad, with the fuse being a silicide electromigration fuse that increases impedance by narrowing through electromigration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each test element is connected to a single pad, then testing accuracy is ensured, but the number of pads increases with the number of test elements, consuming limited semiconductor device space
Solution Approach 1:
A single pad is designed to serve multiple test elements sequentially. The pad structure is configured to accept connections from different test elements at different time points, enabling one pad to perform the testing function for multiple elements rather than requiring dedicated pads for each element.
Solution Approach 2:
The connection between pads and test elements is made dynamic through controllable switches and fuse elements. These components can change their connection state based on testing progress, allowing the pad configuration to be reconfigured for different testing phases, transitioning from static one-to-one connections to dynamic many-to-one connections.
2Productivity
If multiple pads are used to test multiple test elements, then testing efficiency is improved, but the complexity of the device increases due to more interconnect structures
Solution Approach 1:
Multiple test element connections are merged into a single pad through the use of controllable switches and fuse elements. Instead of maintaining separate independent connection paths for each test element, the design combines these paths through shared pad infrastructure controlled by switching mechanisms, reducing the overall number of interconnect structures.
Solution Approach 2:
The testing process is segmented into sequential phases, with each phase dedicated to testing a specific test element. During each phase, only the relevant switch and fuse elements are activated to create the necessary connection, while other elements remain inactive. This temporal segmentation allows complex multi-element testing to be achieved through simpler staged connections.
3Adaptability or versatility
If fuse elements are used to disconnect test elements after testing, then pad reuse is enabled, but additional manufacturing steps and process control are required
Solution Approach 1:
Fuse elements and switch structures are pre-configured and positioned during the semiconductor fabrication process before final device assembly. This preliminary placement of disconnect mechanisms ensures that the infrastructure for pad reuse is already in place, requiring only activation through standard testing procedures rather than additional complex manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient testing of multiple test elements using a limited number of pads by sequentially disconnecting the first test element from the pad after testing, allowing the second test element to be tested without interference, thereby optimizing the use of space on the semiconductor device.
Implementation Method 1
the fuse being a silicide electromigration fuse that increases impedance by narrowing through electromigration
Data Source
AI summary
Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then “cut” by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical “open” (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate.


