Fused Bitwise and FPL Data Path for Multi-Type Neural Network Processing
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Solution Overview
Problem
Existing electronic devices require multiple hardware accelerators to process different data types, leading to increased size, manufacturing cost, and power consumption due to the need for various data types in neural networks like CNN, BNN, and TNN.
Innovation Solution
An electronic device is designed to compute inner products on binary, ternary, non-binary, and non-ternary data using a fused bitwise data path and a Full Precision Layer (FPL) data path, combining these paths to form a Processing Element (PE) that supports both bitwise and full precision operations without additional storage overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple hardware accelerators are implemented to process different data types (binary, ternary, non-binary, non-ternary), then the processing capability and versatility are improved, but the device size, manufacturing cost, and power consumption increase
Solution Approach 1:
The patent implements a universal processing element that can handle multiple data types (binary, ternary, non-binary, non-ternary) through a single hardware accelerator. This is achieved by designing a multi-functional architecture that dynamically adapts to different data types, eliminating the need for separate dedicated accelerators for each data type while maintaining comprehensive processing capability
Solution Approach 2:
The patent merges multiple data type processing capabilities into a single hardware accelerator by combining binary processing units, ternary processing units, and full precision layer units into one integrated structure. This consolidation reduces the overall device size while preserving the ability to process all four data types through shared hardware resources
2Adaptability or versatility
If multiple hardware accelerators are implemented to process different data types, then the processing capability is improved, but the manufacturing cost increases
Solution Approach 1:
The universal processing element reduces manufacturing cost by consolidating multiple specialized accelerators into a single multi-functional unit. This approach decreases the total component count, simplifies the manufacturing process, and reduces assembly complexity while maintaining the ability to process all data types through configurable hardware logic
Solution Approach 2:
By merging binary, ternary, and full precision processing capabilities into one integrated hardware accelerator, the patent reduces the number of separate components that need to be manufactured and assembled. This consolidation directly lowers manufacturing costs through reduced material usage, simpler production workflows, and decreased assembly operations
3Adaptability or versatility
If multiple hardware accelerators are implemented to process different data types, then the processing capability is improved, but the power consumption increases
Solution Approach 1:
The universal processing element reduces power consumption by enabling a single hardware accelerator to dynamically switch between different data type processing modes. This eliminates the need to operate multiple separate accelerators simultaneously, reducing overall power draw while maintaining the capability to process all four data types as needed through configurable operational states
4Area of stationary object
If a single hardware accelerator processes all data types, then the device size and power consumption are reduced, but the processing speed and efficiency may decrease
Solution Approach 1:
The patent employs dynamic configuration within the universal processing element, allowing the hardware accelerator to adapt its internal structure and processing mode based on the input data type. This dynamic reconfiguration enables the single accelerator to optimize its processing speed for each specific data type (binary, ternary, non-binary, non-ternary) while maintaining a compact device size, rather than being locked into a fixed architecture
Data Source
AI summary
A method for computing an inner product on a binary data, a ternary data, a non-binary data, and a non-ternary data using an electronic device. The method includes calculating the inner product on a ternary data, designing a fused bitwise data path to support the inner product calculation on the binary data and the ternary data, designing a FPL data path to calculate an inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data, and distributing the inner product calculation for the binary data and the ternary data and the inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data in the fused bitwise data path and the FPL data path.