Fused Complex Multiply-Add Instruction for Vector Processing

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Solution Overview

Problem

Existing processor instruction set architectures for high-performance computing face inefficiencies in performing complex multiplication and accumulation operations, leading to high register file pressure, memory pressure, and power consumption due to the need for multiple instructions.

Innovation Solution

The introduction of fused complex multiplication and addition instructions that reduce resource usage by performing multiplication of two vectors of complex numbers and accumulation in a single instruction, with options for conjugation and various precision implementations, allowing for reduced register and memory pressure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple separate instructions are used for complex multiplication and accumulation, then operational flexibility is maintained, but register file pressure increases and power consumption rises

Engineering Contradiction:
Improveoperational flexibilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent combines complex multiplication and accumulation operations into a single fused instruction (VCFMADD). This merging eliminates the need for separate multiply and add instructions, reducing the number of instructions executed and thereby lowering power consumption while maintaining full operational flexibility through configurable operands and destinations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The fused complex multiply-add instruction serves multiple functions simultaneously: it performs complex multiplication, complex accumulation, and supports both vector and scalar operations. The instruction can operate on packed complex data elements with configurable vector lengths, providing universal functionality that replaces multiple specialized instructions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If multiple separate instructions are used for complex multiplication and accumulation, then instruction precision is maintained, but the number of required instructions increases

Engineering Contradiction:
Improveinstruction precisionVSAvoidnumber of instructions
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent merges complex multiplication and accumulation into a single atomic instruction that maintains full precision. The fused instruction performs both operations in one execution cycle without intermediate rounding or precision loss, achieving the same numerical accuracy as separate instructions but with half the instruction count.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If traditional complex arithmetic instructions are used, then computational accuracy is maintained, but memory pressure increases

Engineering Contradiction:
Improvecomputational accuracyVSAvoidmemory pressure
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The fused instruction combines multiply and add operations, allowing the processor to compute results and accumulate them directly in destination registers without storing intermediate multiplication results to memory. This eliminates temporary memory accesses while maintaining full computational accuracy through precise floating-point arithmetic.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20240126546A1Systems and methods for executing a fused multiply-add instruction for complex numbers
Publication Date: 2024.04.18 INTEL CORP
  • US20240126546A1 patent drawing
  • US20240126546A1 patent drawing
  • US20240126546A1 patent drawing

AI summary

Disclosed embodiments relate to executing a vector-complex fused multiply-add instruction. In one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers identifies a location storing a packed data comprising at least one complex number, decoding the instruction, retrieving data associated with the first and second source operand identifiers, and executing the decoded instruction to, for each packed data element position of the identified first and second source operands, cross-multiply the real and imaginary components to generate four products: a product of real components, a product of imaginary components, and two mixed products, generate a complex result by using the four products according to the instruction, and store a result to the corresponding position of the identified destination operand.