Fused Floating-Point Adder-Subtractor Circuitry
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Solution Overview
Problem
Floating-point operations in integrated circuits, particularly addition and subtraction, require expensive normalization and alignment of mantissas, leading to inefficiencies in circuit area and operational latency, especially when performed in parallel.
Innovation Solution
The implementation of specialized processing blocks with a floating-point adder-subtractor circuit that includes an alignment block and an adder circuit, allowing for shared alignment and normalization stages between addition and subtraction operations, reducing inefficiencies by directly coupling processing blocks for efficient computation of sums and differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point addition and subtraction operations are performed with separate normalization and alignment stages, then operational accuracy is maintained, but circuit area increases and operational latency increases
Solution Approach 1:
The patent combines the normalization and alignment stages into a single shared circuit that serves both floating-point addition and subtraction operations. The alignment block and adder circuit are designed to handle both operations simultaneously, eliminating the need for separate dedicated circuits for each operation type.
Solution Approach 2:
The specialized processing blocks are designed with universal functionality to perform both addition and subtraction operations using the same hardware resources. The circuit can be configured to perform different operations based on control signals, making the hardware multi-functional rather than requiring separate dedicated circuits.
2Adaptability or versatility
If separate processing blocks are used for floating-point addition and subtraction, then operational flexibility is maintained, but operational latency increases
Solution Approach 1:
The patent merges the addition and subtraction processing blocks into a single specialized processing block that can perform both operations. The shared alignment block and adder circuit are designed to handle both operations in sequence or parallel depending on the operation type, reducing the overall latency compared to separate dedicated blocks.
3Reliability
If full normalization is performed for both addition and subtraction operations, then IEEE 754 standard compliance is maintained, but circuit area increases
Solution Approach 1:
The patent implements a shared normalization circuit that serves both addition and subtraction operations. The same normalization logic and circuitry are reused for both operations, maintaining IEEE 754 compliance while avoiding the area overhead of duplicate normalization circuits.
Data Source
AI summary
An integrated circuit may be provided with a specialized processing block that performs floating-point addition and subtraction operations. For this purpose, the specialized processing block includes a fused adder and subtractor stage with an adder circuit and a subtractor circuit. The adder and subtractor circuits share an alignment stage for aligning the mantissas of incoming floating-point numbers and provide a simplified normalization stage with one right shifter and one left shifter. The specialized processing blocks may be arranged in rows or columns such that an input of a first specialized processing block is directly coupled to an output of a second specialized processing block and an input of the second specialized processing block is directly coupled to an output of the first specialized processing block.