Fused Floating-Point Instructions for Faster Dynamic Programming

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing dynamic programming algorithms on parallel processors suffer from computational inefficiencies due to the sequential execution of multiple instructions and data movement, leading to prolonged computation times, especially in matrix-filling phases for large DNA and protein sequences.

Innovation Solution

Implement specialized instructions, such as a VIMNMX instruction, to concurrently determine and store maximum or minimum sub-alignment scores, reducing the number of instructions required and increasing computational efficiency by using a SIMD staggered thread technique.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple instructions are executed sequentially to determine and store maximum or minimum sub-alignment scores, then the computation is accurate, but the computation time increases and productivity decreases

Engineering Contradiction:
Improvecomputation accuracyVSAvoidcomputation throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent combines multiple sequential instructions (comparison and storage operations) into a single fused instruction that can concurrently determine and store maximum or minimum sub-alignment scores. This merging of operations eliminates the sequential execution bottleneck while maintaining computational accuracy, thereby increasing instruction-level parallelism and computation throughput.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a new dimension of parallelism by implementing fused instructions that operate on multiple data elements simultaneously using SIMD (Single Instruction Multiple Data) staggered thread techniques. This transitions from sequential single-threaded execution to parallel multi-threaded execution, significantly improving productivity without sacrificing accuracy.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the number of instructions is reduced by using specialized fused instructions, then productivity increases, but device complexity increases

Engineering Contradiction:
Improvecomputation throughputVSAvoidinstruction set complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements universal fused instructions that can handle multiple operations (comparison, maximum selection, minimum selection, and storage) within a single instruction format. This multi-functionality reduces the total number of instructions needed while the underlying hardware complexity is managed through standardized instruction decoding and execution units that can handle various operation types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If data is moved between memory and processing units during computation, then computation accuracy is maintained, but computation time increases and productivity decreases

Engineering Contradiction:
Improvecomputation accuracyVSAvoidcomputation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent employs preliminary action by pre-fetching and caching necessary data (sub-alignment scores, gap constants, substitution values) into registers or fast memory before the main computation loop. This allows the fused instructions to operate on data already in fast access memory, eliminating repeated memory access delays while maintaining computational accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuity of useful action by overlapping data movement operations with computation operations using pipelining and staggered thread techniques. While one thread computes, another thread can be loading data, ensuring that the processing units are continuously utilized without idle waiting time for memory operations.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20260064415A1Implementing specialized floating point instructions on an integer pipeline for accelerating dynamic programming algorithms
Publication Date: 2026.03.05 NVIDIA CORP
  • US20260064415A1 patent drawing
  • US20260064415A1 patent drawing
  • US20260064415A1 patent drawing

AI summary

Various techniques for accelerating dynamic programming algorithms are provided. For example, a fused addition and comparison instruction, a three-operand comparison instruction, and a two-operand comparison instruction are used to accelerate a Needleman-Wunsch algorithm that determines an optimized global alignment of subsequences over two entire sequences. In another example, the fused addition and comparison instruction is used in an innermost loop of a Floyd-Warshall algorithm to reduce the number of instructions required to determine shortest paths between pairs of vertices in a graph. In another example, a two-way single instruction multiple data (SIMD) floating point variant of the three-operand comparison instruction is used to reduce the number of instructions required to determine the median of an array of floating point values.