Fused Level-Shifting Latch Circuit for Low-Delay Multi-Voltage ICs
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Solution Overview
Problem
Conventional voltage level shifting circuits and latch circuits in IC devices suffer from higher time delay, limited voltage shifting range, and large size, making them unsuitable for devices operating in multiple voltage domains, particularly in low voltage environments, which can cause functionality failures and performance limitations.
Innovation Solution
A combined voltage level shifting and latch circuit design that integrates both functions into a single circuit, reducing input-to-output time delay, expanding the voltage shifting range, and minimizing circuit size, while ensuring compatibility with existing design synthesis flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate voltage level shifting circuits and latch circuits are used, then the functions are clearly separated and easy to design, but the time delay increases and the circuit size becomes large
Solution Approach 1:
The patent combines the voltage level shifting circuit and latch circuit into a single integrated circuit. The latch circuit is designed to directly accept input signals at a first voltage level and produce output signals at a second voltage level, eliminating the need for separate voltage level shifting and latching stages. This merging reduces the number of circuit stages and interconnections, thereby reducing the overall time delay while maintaining clear functional separation through integrated design.
2Adaptability or versatility
If conventional voltage level shifting circuits are used, then the design is simple, but the voltage shifting range is limited and time delay is high
Solution Approach 1:
The latch circuit employs dynamic circuit elements including transmission gates and cross-coupled logic gates that can adapt their operation based on the voltage levels of input and clock signals. The circuit uses dynamic latching mechanisms that allow it to operate across a wide voltage shifting range by adjusting the conduction states of transmission gates and the switching behavior of logic gates, thereby expanding adaptability while maintaining fast response times through dynamic operation.
3Reliability
If conventional latch circuits are used, then the latching function is reliable, but the circuit size becomes large
Solution Approach 1:
The patent integrates the latching function within the voltage level shifting circuit by using cross-coupled logic gates that serve dual purposes: level shifting and latching. The cross-coupled gates form a latch structure that maintains the latched state while simultaneously performing voltage level conversion. This integration eliminates the need for separate latch circuitry, reducing the overall circuit area while preserving the reliability of the latching function through the inherent feedback mechanism of the cross-coupled gates.
Data Source
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AI summary
Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.