Fused Modular Multiply and Add Operation for Cryptography
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Solution Overview
Problem
Existing computer technologies face inefficiencies in performing modular multiplication and addition operations, which are crucial for applications like cryptography and machine learning, due to the need for multiple separate instructions and increased memory accesses.
Innovation Solution
The implementation of a fused modular multiply and add (FMMA) operation, which combines the modular multiplication and addition into a single instruction, utilizing a set of multiply-and-accumulate units and an adder to efficiently compute the result of ((a*b)+c) % p.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate instructions are used for modular multiplication and addition, then the operations can be performed with standard hardware, but the number of instructions and memory accesses increases, reducing execution efficiency
Solution Approach 1:
The patent combines modular multiplication and addition into a single fused instruction (FMMA) that executes both operations atomically. The instruction format includes operands a, b, c, and modulus p, with the computation d = ((a × b) + c) mod p performed in one execution cycle, eliminating the need for separate MUL and ADD instructions and reducing memory accesses.
Solution Approach 2:
The fused modular multiply-add unit is designed to handle both multiplication and addition operations within a single hardware structure. The same computational units (multipliers and adders) are utilized for both operations, allowing the hardware to perform multiple functions efficiently without requiring separate dedicated circuits for each operation type.
2Loss of time
If multiple separate operations are used, then hardware resources can be shared, but the number of memory accesses increases, increasing latency
Solution Approach 1:
The patent loads all required operands (a, b, c, and p) into register files before the FMMA instruction executes. This preliminary loading ensures that all data is available in fast register memory when the fused operation begins, eliminating the need for additional memory accesses during the actual computation and reducing overall latency.
3Speed
If standard separate operations are used, then implementation is simpler, but execution speed is slower due to sequential processing
Solution Approach 1:
The fused modular multiply-add operation enables continuous computation by eliminating the sequential gap between multiplication and addition. The hardware pipeline processes the FMMA instruction in a single continuous flow, with the multiplication result immediately fed into the addition unit without intermediate storage or control overhead, maximizing throughput and execution speed.
Data Source
AI summary
A computer-implemented method includes receiving performing a fused modular multiply and add operation to compute d=((a*b)+c) % p, wherein a, b, and c, are provided as a set of operands. A first multiply-and-accumulate unit computes a binary multiplication to compute a*b. A second multiply-and-accumulate unit computes a first intermediate result by updating a result of the binary multiplication using p. An accumulator of a third multiply-and-accumulate unit is initialized with c. The third multiply-and-accumulate unit computes a second intermediate result using the first intermediate result and c. An adder unit subtracts a portion of the second intermediate result from a portion of the result of the binary multiplication. The output of the adder is provided as a result of the fused modular multiply and add operation.