Fused Multiply-Adder Booth Encoding Multi-Precision
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Solution Overview
Problem
Existing fused multiply-adder circuits face challenges in efficiently handling multiple precisions of floating-point numbers, either requiring separate data paths for each precision, leading to increased chip area, or utilizing only half the operand bandwidth when handling single-precision numbers.
Innovation Solution
A fused multiply-adder design incorporating a Booth encoder, fraction multiplier, carry corrector, and adder, which operates in full-precision or two-way mode, using guard zeros to maintain precision and apply carry correction factors to ensure accurate results across different precision levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate data paths are used for each number precision, then multiple precision operations can be executed simultaneously, but chip area increases
Solution Approach 1:
The patent implements a universal data path that can handle both single-precision and double-precision operations using the same hardware resources. The fused multiply-adder is designed with configurable width and precision settings, allowing it to perform different precision operations sequentially without requiring separate dedicated paths for each precision level.
Solution Approach 2:
The data path is designed to be dynamically reconfigurable between single-precision and double-precision modes. The circuit can adjust its operational parameters and internal configuration based on the input precision requirements, enabling flexible resource utilization while maintaining support for multiple precision operations.
2Area of stationary object
If a single data path is used for both single- and double-precision numbers, then chip area is reduced, but only half the operand bandwidth is utilized when handling single-precision numbers
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the operational precision and data width of the single data path based on input requirements. When single-precision operations are detected, the circuit configures itself to operate at optimal single-precision parameters, effectively utilizing the full bandwidth for that precision level rather than being constrained by double-precision width requirements.
Solution Approach 2:
The data path is segmented into configurable stages that can be independently optimized for different precision levels. This segmentation allows the circuit to activate only the necessary portions of the data path for each operation type, maximizing bandwidth utilization while avoiding the waste of using full double-precision width for single-precision operations.
3Productivity
If Booth encoding is applied to multiplication, then multiplication efficiency is improved, but carry correction complexity increases
Solution Approach 1:
The patent applies preliminary action by performing Booth encoding on the operands before multiplication to reduce the number of partial products and simplify the multiplication process. Additionally, carry correction factors are pre-calculated and prepared in advance based on the Booth-encoded values, so that when the multiplication is complete, the carry correction can be applied directly without complex real-time calculations.
Solution Approach 2:
The patent introduces carry correction factors as an intermediary element that mediates between the Booth-encoded multiplication result and the final accurate result. These correction factors are generated based on the Booth encoding properties and are used to adjust the partial sums, simplifying the overall carry correction process while maintaining multiplication efficiency.
Data Source
AI summary
A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.