Fused Processing Register Sharing for Matrix Data Movement
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Solution Overview
Problem
The performance of high-density computing operations such as matrix multiplications in Deep Learning and High Performance Computing workloads is limited by the rate at which data can be fed into execution units, constrained by the width and speed of buses connecting execution units and shared local memory.
Innovation Solution
Implementing techniques to improve data transfer speeds between memory and execution units by sharing register file usage between fused processing resources, including graphics processing units and general-purpose processors, to optimize data movement and enhance computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer between memory and execution units is performed through conventional buses, then system complexity is maintained at acceptable levels, but data transfer speed becomes a bottleneck limiting computational performance
Solution Approach 1:
The patent merges the register files of the first and second processing resources into a shared register file, allowing both execution units to access the same register storage. This consolidation eliminates redundant register files, reduces overall system complexity, and enables more efficient data sharing between processing resources, thereby improving computational performance without requiring increased data transfer speeds through broader buses.
Solution Approach 2:
The shared register file serves multiple functions: it acts as the register file for the first execution unit, the register file for the second execution unit, and a shared data buffer between the two processing resources. This multi-functionality allows the same hardware structure to support multiple processing operations simultaneously, improving productivity while maintaining acceptable system complexity.
2Reliability
If dedicated register files are provided for each execution unit, then data access reliability is improved, but device complexity increases and resources are underutilized
Solution Approach 1:
The patent combines separate register files into a single shared register file that serves multiple execution units. This merging reduces device complexity by eliminating redundant register file structures while maintaining data access reliability through shared access control and consistent address mapping mechanisms that ensure each execution unit can reliably access its required data.
Solution Approach 2:
The shared register file is designed to universally serve multiple execution units through a unified interface and address decoding scheme. This universal structure reduces complexity compared to multiple dedicated register files while maintaining reliability by providing consistent data access guarantees to all executing units that require it.
Data Source
AI summary
Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.