Fused Scalar Instruction Pairing for Higher VSU Throughput
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Solution Overview
Problem
Modern processors face challenges in efficiently executing scalar instructions due to limited processing power and register file management, leading to inefficiencies in register tag allocation and potential collisions.
Innovation Solution
The proposed solution involves fusing adjacent scalar instructions into a pair, assigning register tags, and executing them simultaneously through vector-scalar transformation units (VSU) to enhance execution rate without additional processing pipes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scalar instructions are processed one piece of data at a time using traditional scalar processors, then the processing approach is simple and straightforward, but the execution rate is low compared to vector processors
Solution Approach 1:
The patent combines scalar and vector processing capabilities into a unified VSU (Vector-Scalar Transformation Unit). The VSU can dynamically switch between executing scalar instructions (one data element at a time) and vector instructions (multiple data elements simultaneously), merging the simplicity of scalar processing with the high throughput of vector processing in a single hardware unit, thereby increasing scalar instruction execution rate without requiring separate processing pipelines
Solution Approach 2:
The VSU is designed as a universal processing unit that can handle both scalar and vector operations. It includes configurable execution ports that can be dynamically allocated based on the instruction type and data availability, allowing the same hardware resource to serve multiple processing functions and achieve higher overall productivity without proportionally increasing device complexity
2Productivity
If additional VSU processing pipes are added to increase scalar instruction execution rate, then the execution rate increases, but the device complexity and resource requirements increase
Solution Approach 1:
The VSU employs dynamic resource allocation where execution ports and processing resources are not statically assigned but are dynamically configured based on the current instruction stream and data availability. The unit can adaptively switch between scalar and vector modes, and dynamically allocate execution ports to maximize throughput without requiring dedicated processing pipes for each mode, thereby increasing execution rate while controlling device complexity
Solution Approach 2:
The VSU changes its operational parameters dynamically, including the number of active execution ports, the data element width, and the operation mode (scalar vs. vector). By adjusting these parameters based on the instruction characteristics and available data, the system can optimize performance for different workloads without requiring additional fixed processing pipes, achieving higher productivity with controlled complexity
Data Source
AI summary
A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with two register tags, write the two register tags into a mapper, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation unit (VSU), and execute the two instructions.