Fused Store Exclusive and Memory Barrier Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multiprocessor and multithreaded environments, spin locks using load exclusive, store exclusive, and data memory barrier instructions lead to performance degradation due to long latency and synchronization issues, affecting the predictability and efficiency of critical region access in processors.
Innovation Solution
A processor is configured to fuse the store exclusive operation with the data memory barrier operation, creating a combined operation that is transmitted and globally ordered, reducing latency by ensuring both operations are completed in response to the fused operation, and pushing previous memory operations to the memory barrier point for global visibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate store exclusive and data memory barrier operations are executed, then correct spin lock operation is ensured, but processor performance degrades due to long latency and multiple synchronization points
Solution Approach 1:
The patent combines the store exclusive operation and data memory barrier operation into a single fused operation. The load/store unit detects when a store exclusive operation is followed by a data memory barrier operation and issues them as one combined operation to the cache hierarchy. This reduces the number of separate synchronization points, decreases latency, and improves processor performance while maintaining correct spin lock operation through the unified operation's global ordering guarantee.
2Stability of the object's composition
If multiple separate memory operations are used for spin lock, then global ordering is ensured, but the number of operations increases leading to higher latency
Solution Approach 1:
The patent merges the store exclusive operation and data memory barrier operation into a single fused operation that maintains global ordering. The unified operation ensures that all previous memory operations are pushed to the ordering point while completing both the store exclusive and memory barrier functions in one synchronized step, thereby reducing latency without compromising global ordering stability.
Solution Approach 2:
The load/store unit performs preliminary detection and fusion of the store exclusive and data memory barrier operations before they reach the cache hierarchy. By preparing and combining these operations in advance at the load/store unit, the system reduces the number of separate transmission steps to the ordering point, thereby decreasing overall latency while ensuring global ordering is maintained.
Data Source
AI summary
In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier operation, creating a fused operation. The fused operation may be transmitted and globally ordered, and the processor may complete both the store exclusive operation and the memory barrier operation in response to the fused operation. As the fused operation progresses through the processor and one or more other components (e.g. caches in the cache hierarchy) to the ordering point in the system, the fused operation may push previous memory operations to effect the memory barrier operation. In some embodiments, the latency for completing the store exclusive operation and the subsequent data memory barrier operation may be reduced if the store exclusive operation is successful at the ordering point.