Fused Store Microinstruction Dispatch in Microprocessor Reorder Buffer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Microprocessors with CISC macroarchitectures face inefficiencies in executing frequently occurring store macroinstructions, which are not executed quickly enough due to the complexity of translating these instructions into simpler microinstructions.
Innovation Solution
The microprocessor employs an instruction translator to break down store macroinstructions into fused store microinstructions, which are then dispatched to different execution units without occupying reorder buffer entries, allowing for simultaneous execution of store address and data microinstructions, thereby optimizing execution speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If store macroinstructions are translated into separate microinstructions using conventional methods, then the instructions can be executed, but the execution speed is insufficient due to the complexity of the translation process and the load on the reorder buffer
Solution Approach 1:
The patent merges the store address microinstruction and store data microinstruction into a single fused store microinstruction. This fusion eliminates the need for separate microinstructions, reducing the complexity of the translation process and enabling faster execution of store macroinstructions while maintaining the necessary functionality of both address calculation and data storage operations
Solution Approach 2:
The fused store microinstruction is segmented into distinct functional fields within a single instruction structure. The instruction includes separate fields for store address operands and store data operands, allowing the execution unit to efficiently extract and process both address and data components simultaneously without requiring multiple separate microinstructions
2Productivity
If separate store address and store data microinstructions are used, then the operations can be performed, but the reorder buffer becomes overloaded and execution efficiency decreases
Solution Approach 1:
By combining two separate microinstructions (store address and store data) into a single fused store microinstruction, the patent reduces the quantity of microinstructions that need to be managed in the reorder buffer. This fusion decreases the load on the ROB, allowing more instructions to be processed efficiently and improving overall execution productivity
Data Source
AI summary
A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register into and mask off bits in a temporary register, and the fused store microinstruction stores it to a memory location. For POP, a first microinstruction loads a first memory location value into a temporary register and the fused store microinstruction stores it to the second memory location. For MOVSB, the first microinstruction loads a first memory location operand into a temporary register and the fused store microinstruction stores it to a second memory location. A reorder buffer receives the fused store microinstruction into exactly one entry. In response to the fused store microinstruction, an instruction dispatcher dispatches store address and store data microinstructions, neither of which occupies a reorder buffer entry, to different respective execution units.