Fusible I/O Interconnection for Flip-Chip Packaging
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Solution Overview
Problem
Conventional chip packaging methods, such as wire bonding and solder-bump techniques, face challenges including low throughput, reliability issues due to fine pitch requirements, and the use of lead-containing solder, which can lead to contamination and increased costs.
Innovation Solution
The method involves forming stud-bumps on a substrate and attaching a chip to these bumps using under-bump metallization and a fusible material, allowing for finer pitch connections and eliminating the need for solder balls, thereby reducing contamination risks and streamlining the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wire bonding is used to make electrical connections, then electrical connectivity is achieved, but throughput is low due to serial pad-by-pad processing
Solution Approach 1:
The invention segments the connection process by forming discrete bumps at each pad location before die attachment. These pre-formed bumps serve as individual connection points that enable parallel processing during the bump formation stage, thereby increasing throughput while maintaining organized connection structures.
Solution Approach 2:
The invention performs preliminary bump formation on the substrate before die attachment. By pre-forming the bumps with conductive material at their final locations, the subsequent die attachment process becomes simpler and can proceed in parallel across multiple connections, significantly improving throughput compared to serial wire bonding.
2Quantity of substance
If the number of I/O connections is increased, then connectivity is improved, but pitch must be reduced which decreases reliability
Solution Approach 1:
The invention transitions from planar wire bonding to three-dimensional bump structures. By forming vertical bumps that rise from the substrate surface, the connection points occupy additional vertical space, allowing higher density connections without reducing the horizontal pitch between adjacent connections, thereby maintaining reliability while increasing the number of I/O connections.
3Ease of manufacture
If solder balls are used for connections, then electrical connectivity is achieved, but lead contamination occurs and costs increase
Solution Approach 1:
The invention extracts the harmful lead component from the connection structure by replacing solder balls with bumps formed from lead-free conductive materials. The bumps are created through deposition processes using materials such as copper, aluminum, or other non-toxic conductive materials, eliminating lead contamination while maintaining electrical connectivity and manufacturing simplicity.
Solution Approach 2:
The invention changes the material parameter of the connection structure from lead-based solder to lead-free conductive materials. By altering the compositional parameters to use environmentally friendly materials with equivalent or superior electrical and mechanical properties, the invention eliminates contamination risks while preserving manufacturing ease.
4Quantity of substance
If finer pitch connections are made, then more I/O connections fit on the chip, but manufacturing precision requirements increase
Solution Approach 1:
The invention performs preliminary bump formation with precise positioning on the substrate before die attachment. By pre-establishing the bump locations and dimensions with controlled deposition processes, the subsequent die placement can rely on these pre-formed features as registration points, reducing the precision burden on the final assembly step while enabling finer pitch connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more efficient and reliable electrical connections with finer pitches, reduces contamination risks by eliminating lead, and simplifies the manufacturing process by separating wafer-fabrication and assembly steps, leading to lower costs and improved device performance.
Implementation Method 1
at least a portion of the fusible material is caused to flow to and make a connection with the corresponding bond-pads on the chip
Implementation Method 2
forming under-bump metallization (UBM) on each of the I/O bond-pads on the chip
Data Source
AI summary
A semiconductor device has a semiconductor die with bond pads formed on a surface of the semiconductor die. A UBM is formed over the bond pads of the semiconductor die. A fusible layer is formed over the UBM. The fusible layer can be tin or tin alloy. A substrate has bond pads formed on a surface of the substrate. A plurality of stud bumps containing non-fusible material is formed over the bond pads on the substrate. Each stud bump includes a wire having a first end attached to the bond pad of the substrate and second end of uniform height electrically connected to the bond pad of the semiconductor die by reflowing the fusible layer or applying thermal compression bonding. An underfill material is deposited between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and substrate.