Fusible Logic Array for Security Chip Authentication

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Solution Overview

Problem

Systems-on-chips (SoCs) are vulnerable to reverse engineering techniques that allow counterfeit chips to be created, which can replicate the functionality and identity of original chips, posing a threat to security and authenticity.

Innovation Solution

A security chip with a fusible logic array that generates keys from seed values and stores seed-key pairs, using programmable fusible links to create a hidden logic function, making it difficult to ascertain the logic operations and thus hindering counterfeiting attempts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional security measures are used to protect chip authenticity, then basic counterfeit prevention is achieved, but advanced reverse engineering techniques can still extract secret information and create functional copies

Engineering Contradiction:

Improvechip authenticity protectionVSAvoidreverse engineering capability

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a fusible logic array as an intermediary component between the seed input and key output. This array contains programmable fusible links that act as a mediator, transforming the input seed through a hidden logic function to produce the output key. The fusible links serve as the intermediary element that obscures the relationship between input and output, preventing direct analysis while maintaining functional correctness.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the physical state of the fusible links from unfused to fused through programmable melting. This parameter change (from conductive to non-conductive state) permanently configures the logic function of the array. By changing the physical state of these links during manufacturing or initialization, the system creates a unique, non-replicable logic configuration that protects against reverse engineering while maintaining reliable authentication functionality.

Inventive Principle:

Principle #35Parameter changes

2Object-affected harmful factors

If a fusible logic array with programmable fusible links is implemented to hide logic functions, then resistance to reverse engineering is improved, but device complexity increases

Engineering Contradiction:

Improvereverse engineering resistanceVSAvoidlogic array structure

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent segments the authentication logic into two separate components: a fusible logic array for key generation and a challenge-response verification module for authentication. This segmentation allows the complex key generation function to be isolated in the fusible array, while the verification logic remains simple and reusable. The segmentation reduces overall system complexity by dividing functions into manageable, specialized modules.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The fusible logic array is programmed with its specific logic function through preliminary action during manufacturing or initialization. The fusible links are melted in specific patterns to establish the desired logic connections before the chip enters service. This preliminary configuration eliminates the need for complex runtime logic, simplifying the operational complexity of the device while maintaining high reverse engineering resistance.

Inventive Principle:

Principle #10Preliminary action

3Ease of operation

If seed-key pairs are stored in memory for verification, then authentication capability is improved, but security vulnerability to extraction attacks increases

Engineering Contradiction:

Improveauthentication capabilityVSAvoidextraction attack vulnerability

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the secret key from the verification process and replaces it with a public challenge-response mechanism. Instead of storing and using secret keys in memory for verification, the system extracts only the necessary verification functionality. The fusible logic array generates keys on-demand from seeds, and only the verification logic (not the keys themselves) is stored in memory, reducing the attack surface for extraction attacks.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses disposable, non-replicable fusible links to create a unique logic function in each chip. These fusible links are destroyed during programming to establish the logic configuration, making each chip's authentication logic unique and non-replicable. This approach replaces expensive, vulnerable stored keys with cheap, non-replicable physical structures that cannot be extracted or copied.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS9660802B1Systems and methods for generating and storing silicon fingerprints for a security chip

Publication Date: 2017.05.23 MARVELL ASIA PTE LTD

AI summary

A security chip including a fusible logic array. The fusible logic array is configured to receive a plurality of seed values and output a plurality of respective keys using the received plurality of seed values. The respective keys correspond to logic results generated by the fusible logic array. The fusible logic array includes one or more fusible links. A key storage control module is configured to receive the plurality of seed values, receive the plurality of respective keys, and store, in memory, a selected first seed value of the plurality of seed values and a selected first key of the plurality of respective keys. The selected first seed value and the selected first key are stored as a seed-key pair.