Fusion-Bonded Die Stack Packaging Without TSV Interposers
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Solution Overview
Problem
The semiconductor industry faces challenges in bonding integrated circuit dies directly onto substrates due to increased density and shrinking device sizes, requiring innovative packaging techniques that incorporate three-dimensional aspects to enhance functionality and reduce footprint.
Innovation Solution
A die stack is formed by stacking integrated circuit dies in a back-to-face manner without solder, using fusion bonding and redistribution structures with fine-pitched metallization patterns to interconnect the dies, eliminating the need for through substrate vias and packaging interposers, thereby reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If integrated circuit dies are directly bonded onto substrates using conventional techniques, then bonding can be achieved, but the process becomes increasingly difficult and costly as integration density increases and device sizes shrink
Solution Approach 1:
The patent transitions from conventional 2D planar bonding to 3D vertical stacking architecture. Multiple integrated circuit dies are stacked vertically and bonded face-to-face, creating a three-dimensional integrated circuit package. This dimensional change allows higher integration density without increasing the lateral footprint, and enables bonding processes to be performed more easily in the vertical direction rather than requiring precise lateral alignment of increasingly small components.
2Area of moving object
If three-dimensional stacking is implemented to reduce footprint, then device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit package into discrete stacked layers or dies, where each die can be independently fabricated, tested, and processed. This segmentation allows complex 3D integration to be achieved through repeated application of simpler bonding operations between individual layers, rather than attempting to create the entire complex structure in a single process step.
Solution Approach 2:
The patent performs preliminary fabrication and testing of individual dies before stacking them together. Each die is completely processed and validated independently prior to bonding, which simplifies the overall manufacturing process by separating complex fabrication steps from the bonding process. This preliminary action ensures that each component is ready for assembly, reducing the complexity of the integration process.
3Quantity of substance
If conventional bonding techniques are used, then integration can be achieved, but integration density cannot keep pace with component shrinkage
Solution Approach 1:
The patent employs 3D vertical stacking to achieve higher integration density by utilizing the vertical dimension in addition to the lateral plane. As minimum feature sizes shrink, the lateral area available for integration decreases, but the vertical stacking approach allows multiple dies to be integrated in the Z-direction, effectively decoupling integration density from lateral feature size and enabling continued scaling of integration capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, high-functional semiconductor devices with reduced manufacturing costs by directly bonding integrated circuit dies and using redistribution structures for electrical interconnection, facilitating the production of smaller, more efficient electronic components.
Implementation Method 1
A die stack is formed by stacking integrated circuit dies in a back-to-face manner without solder, using fusion bonding
Data Source
AI summary
In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.