Fusion-Bonded 3D Memory Stack for Wide-IO Capacity Limits
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Solution Overview
Problem
Conventional DRAM structures face a trade-off between increasing external bandwidth and maintaining total memory capacity within a given x-y form factor, leading to decreased memory capacity as die size increases to accommodate pin placement and routing.
Innovation Solution
A fusion bonded 3D stacked wide-IO memory structure is implemented, utilizing a via-last approach to achieve high-bandwidth and high-capacity memory with a compact form factor, combining face-to-face fusion bonding and a reduced cost wafer stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If die size is increased to accommodate pin placement and routing for higher external bandwidth, then external bandwidth is improved, but total memory capacity decreases within a given x-y form factor
Solution Approach 1:
The patent transitions from a 2D planar arrangement to a 3D stacked architecture by bonding multiple memory dies vertically. This dimensional change allows memory capacity to scale in the z-direction (vertical stacking) while maintaining a compact x-y footprint, thereby preserving high memory capacity without sacrificing external bandwidth achieved through wide I/O on each die
2Quantity of substance
If 3D stacked memory structure is implemented to increase memory capacity in compact form factor, then memory capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The memory system is segmented into multiple independent dies that can be fabricated separately using conventional processes, then bonded together. Each die maintains standard I/O configurations, allowing modular assembly and simplifying the overall manufacturing workflow compared to creating a single complex monolithic structure
Solution Approach 2:
Instead of bonding dies face-to-face (front surfaces together), the patent employs back-to-back bonding where opposite faces (back surfaces) are bonded together. This inversion simplifies the bonding process by accessing and preparing the back surfaces of dies, which are otherwise less constrained during fabrication, thereby reducing manufacturing complexity
3Reliability
If hybrid bonding is used to achieve high-performance 3D stacking, then electrical performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs conventional bonding techniques (such as eutectic bonding or sintering) that use simpler, more cost-effective materials and processes compared to hybrid bonding. While hybrid bonding offers superior electrical performance, the conventional bonding approach provides adequate performance at significantly lower manufacturing cost, making it economically viable for mass production
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides an extremely wide-IO structure with high memory capacity in a small x-y form factor, achieving approximately 12 GB in a memory package size equivalent to conventional LPDDR5x, while reducing costs compared to hybrid bonding.
Implementation Method 1
a back side of the second memory chip is coupled to a back side of the third memory chip through fusion bonding
Data Source
AI summary
A device comprising a memory device comprising: a first memory chip; a second memory chip coupled to the first memory chip, wherein a front side of the first memory chip is coupled to a front side of the second memory chip; a third memory chip coupled to the second memory chip, wherein a back side of the second memory chip is coupled to a back side of the third memory chip through fusion bonding; and a fourth memory chip coupled to the third memory chip, wherein a front side of the third memory chip is coupled to a front side of the fourth memory chip.