Fusion Memory Integrating NAND and DRAM on Single Substrate
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Solution Overview
Problem
NAND flash memories lack high-speed buffer capabilities due to the absence of large capacitance capacitor elements, leading to slow access and write speeds, and the integration of DRAM cells requires significant changes in manufacturing processes, increasing costs and chip area.
Innovation Solution
A fusion memory system is developed, combining a NAND cell unit with a DRAM cell on the same semiconductor substrate, using a MOS capacitor and cell transistor configuration similar to the NAND cell, allowing for high-speed operation without the need for trench or stacked capacitors, thus enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM cells are integrated into NAND flash memory to provide high-speed buffer capabilities, then access speed and write speed are improved, but manufacturing process complexity increases significantly
Solution Approach 1:
The patent merges NAND flash memory and DRAM cells into a single fusion memory structure, where the DRAM cell shares the same semiconductor substrate and manufacturing process as the NAND flash memory. This integration allows the system to achieve high-speed buffer capabilities while avoiding the need for separate DRAM fabrication processes, thereby reducing manufacturing complexity.
Solution Approach 2:
The fusion memory structure is designed to serve multiple functions: it can operate as both NAND flash memory for non-volatile storage and as DRAM for high-speed volatile storage. The same basic cell structure supports both memory types, enabling a single manufacturing process to produce a multi-functional memory device that addresses both speed and cost requirements.
2Productivity
If DRAM cells are integrated into NAND flash memory to provide high-speed buffer capabilities, then write speed is improved, but chip area increases
Solution Approach 1:
The patent combines NAND flash memory and DRAM cells in a unified structure where both memory types share common substrates and manufacturing processes. This merging allows the high-speed buffer function to be integrated without requiring separate DRAM chip area, as the DRAM cells are formed using the same fabrication steps as the NAND flash memory cells.
Solution Approach 2:
The fusion memory structure utilizes vertical stacking and three-dimensional arrangements to pack both NAND flash and DRAM cells within the same chip footprint. By transitioning from a two-dimensional layout to a three-dimensional structure, the patent achieves high-density integration that provides sufficient buffer capacity without proportionally increasing chip area.
3Speed
If conventional DRAM cells are used in NAND flash memory, then high-speed buffer operation is achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent designs a universal cell structure that can function as both NAND flash memory and DRAM using the same manufacturing process. This eliminates the need for separate, expensive DRAM fabrication lines and allows existing NAND flash manufacturing facilities to produce high-speed buffer memory at lower costs. The same deposition, etching, and doping steps create both memory types.
Solution Approach 2:
The patent achieves DRAM-like high-speed operation by modifying parameters within the existing NAND flash manufacturing process, such as adjusting capacitor geometry and transistor dimensions, rather than requiring fundamentally different fabrication techniques. These parameter adjustments enable high-speed buffer operation while maintaining compatibility with standard NAND flash production methods, thereby reducing manufacturing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fusion memory system enhances data transfer speeds and reduces manufacturing costs by utilizing the same process as NAND flash memory, providing a high-capacity buffer with reduced chip area and improved system properties.
Implementation Method 1
using a MOS capacitor and cell transistor configuration similar to the NAND cell
Data Source
AI summary
According to one embodiment, there is provided a fusion memory including a first memory cell array formed of a NAND cell unit and a second memory cell array formed of a DRAM cell on a semiconductor substrate. The NAND cell unit is formed of a non-volatile memory cell having a two-layer gate structure in which a first gate and a second gate are stacked, and a selective transistor connecting the first and second gates of the non-volatile memory cell. The DRAM cell is formed of a cell transistor having a structure same as the structure of the selective transistor, and a MOS capacitor having a structure same as the structure of the non-volatile memory cell or the selective transistor.