GOA Circuit Reliability via Dual Pull-Down Segmentation

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Solution Overview

Problem

The existing Gate Driver on Array (GOA) circuit in display technology faces issues where if one of the alternately operated pull-down circuits in the shift register unit is damaged, the entire circuit fails to work properly, leading to reduced TFT characteristics and lifetime.

Innovation Solution

A display driving circuit with a characteristic collector, comparator, and timing controller is introduced, which includes at least two cascade shift register units with separate pull-down circuits and pull-up voltage terminals. The characteristic collector outputs a characteristic voltage to the comparator, which compares it with a reference voltage, generating a timing control signal to ensure both pull-down circuits are in a working state, even if one is damaged.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple alternately operated pull-down circuits are provided in one shift register unit, then the reliability of the GOA circuit is improved, but the device complexity increases

Engineering Contradiction:
ImproveGOA circuit reliabilityVSAvoidshift register unit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The pull-down function is segmented into multiple independent pull-down circuits (first pull-down circuit and second pull-down circuit) within each shift register unit. Each circuit can operate independently, so when one fails, the other can take over to maintain circuit functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention dynamically switches between alternate operation mode and simultaneous operation mode of pull-down circuits based on their working status. The timing controller adjusts the operation mode in real-time to ensure circuit reliability while managing complexity.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If a single pull-down circuit is provided in the shift register unit, then the device complexity is reduced, but the lifetime of the GOA circuit is reduced due to prolonged TFT ON state

Engineering Contradiction:
Improveshift register unit complexityVSAvoidGOA circuit lifetime
Core Design Contradiction:
Device complexityVSDuration of action of stationary object

Solution Approach 1:

Multiple pull-down circuits operate alternately in periodic cycles, with each circuit being activated for a portion of the time and then deactivated. This periodic switching reduces the cumulative ON time for each individual TFT in the pull-down circuits, thereby extending their operational lifetime.

Inventive Principle:
Principle #19Periodic action

3Reliability

If multiple alternately operated pull-down circuits are provided, then the GOA circuit reliability is improved, but the difficulty of detecting and measuring circuit status increases

Engineering Contradiction:
ImproveGOA circuit reliabilityVSAvoidpull-down circuit status detection
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The timing controller continuously monitors the working status of pull-down circuits and receives feedback signals indicating their operational state. Based on this feedback, the timing controller automatically adjusts the operation mode (alternate or simultaneous) to maintain reliability while simplifying status detection.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10255870B2Display driving circuit, its control method and display device
Publication Date: 2019.04.09 BOE TECHNOLOGY GROUP CO LTD
  • US10255870B2 patent drawing
  • US10255870B2 patent drawing
  • US10255870B2 patent drawing

AI summary

The display driving circuit according to an embodiment of the present disclosure includes a characteristic collector, a comparator, a timing controller and a gate driver. The gate driver includes shift register units each including a first pull-down circuit and a second pull-down circuit, and is provided with a first pull-up voltage terminal and a second pull-up voltage terminal; the characteristic collector is configured for collecting a voltage of the first pull-up voltage terminal or the second pull-up voltage terminal, and for outputting a characteristic voltage; the comparator is configured for comparing the characteristic voltage with a reference voltage of a reference voltage terminal; when the comparison result indicates that the characteristic voltage is greater than or equal to the reference voltage, the timing controller generates a timing control signal such that the first pull-up voltage terminal and the second pull-up voltage terminal are caused to output a DC voltage under the control of the timing control signal.