Gate Driver on Array Circuit for Narrow Frame LCD Panels
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Solution Overview
Problem
Existing gate driver on array (GOA) circuits occupy large space, making it difficult to design liquid crystal display panels with narrow frames.
Innovation Solution
A GOA circuit comprising a first driver module for odd-numbered rows and a second driver module for even-numbered rows, utilizing PMOS and NMOS transistors, inverting amplifiers, and clock inverters/transmission gates to generate and transmit scan drive signals efficiently, with a common clock signal applied to both modules to reduce space occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a conventional GOA circuit with cascade signal latch module, gate drive signal generation module, and gate drive signal output module is used, then the scan lines can be driven sequentially, but the circuit occupies a large space making narrow frame design difficult
Solution Approach 1:
The patent combines the cascade signal latch function and gate drive signal generation function into a single integrated module. The cascade signal latch unit includes transistors that simultaneously perform signal latching and gate drive generation, eliminating the need for separate modules and reducing overall circuit area while maintaining sequential scan line driving capability
Solution Approach 2:
The cascade signal latch unit is designed to perform multiple functions: it latches cascade signals from previous stages, generates cascade drive signals for current stage, produces reset signals, and outputs present stage cascade signals. This multi-functional design reduces the number of dedicated modules needed, thereby reducing the GOA circuit area
2Reliability
If multiple thin film transistors are used in each module of the GOA circuit, then the circuit functionality is complete, but the space occupancy increases
Solution Approach 1:
The GOA circuit is segmented into alternating first driver modules (for odd rows) and second driver modules (for even rows). Each module is further segmented into functional units with specific transistor assignments. This segmentation allows optimized transistor usage in each segment while maintaining overall circuit functionality across all pixel rows
Solution Approach 2:
Different transistor configurations are applied to different parts of the circuit based on functional requirements. The cascade signal latch unit uses specific transistor connections for signal latching, while the output unit uses different configurations for signal generation. This localized optimization ensures each area uses the minimum necessary transistors for its specific function
Data Source
AI summary
A gate driver on array circuit includes a first driver module and a second driver module. The first driver module includes a first driver unit, a first output unit, and a first reset unit. The second driver module includes a second driver unit, a second output unit, and a second reset unit. The first output unit is used for generating a present stage scan drive signal and a present stage cascade signal. The second output unit is used for generating the present stage scan drive signal and the present stage cascade signal.