GOA Shift Register Circuit Structure Simplification
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Solution Overview
Problem
The existing Gate Driver on Array (GOA) technology for display panels has a complex structure due to the high number of thin film transistors, which hinders the design of high-resolution and narrow-frame displays, and lacks a simplified structure for efficient bezel design.
Innovation Solution
A shift register and gate driving circuit are designed with an input sub-circuit, an output sub-circuit, and a pull-down sub-circuit, connected through specific clock signal terminals and power supply terminals, simplifying the GOA circuit structure and enabling a narrow bezel design by controlling signal flow and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional GOA technology is used with multiple thin film transistors per stage, then the gate driving function is achieved, but the circuit structure becomes complex and occupies excessive area
Solution Approach 1:
The patent divides the traditional multi-transistor GOA circuit into three functional sub-circuits: input sub-circuit (first transistor), output sub-circuit (second transistor and capacitor), and pull-down sub-circuit (third transistor). This segmentation allows each sub-circuit to perform a specific function with minimal components, reducing overall complexity while maintaining driving capability.
Solution Approach 2:
The patent merges multiple transistor functions into a coordinated three-transistor system where the first transistor controls signal input, the second transistor controls clock signal output, and the third transistor handles pull-down operations. This merging approach consolidates the gate driving function into a compact structure that occupies less area compared to traditional designs.
2Reliability
If more thin film transistors are used in GOA circuits to ensure proper signal control, then signal control reliability is improved, but the number of transistors increases making the structure more complex
Solution Approach 1:
Each transistor in the patent performs multiple functions: the first transistor serves as both an input switch and a signal level controller; the second transistor functions as both an output driver and a clock signal generator; the third transistor acts as both a pull-down element and a reset mechanism. This multi-functionality ensures reliable signal control with minimal transistor count.
Solution Approach 2:
The patent introduces a capacitor as an intermediary element that stores and transfers signal states between transistor stages. This capacitor mediates the interaction between the input and output sub-circuits, ensuring reliable signal control without requiring additional transistors for signal latching or level shifting.
3Productivity
If the GOA circuit structure is simplified to reduce transistor count, then manufacturing cost and productivity are improved, but the design space for high-resolution and narrow-frame displays is limited
Solution Approach 1:
The patent reorganizes the circuit layout by dividing it into three vertical sub-circuits (input, output, pull-down) that can be arranged in different spatial configurations. This dimensional reorganization allows the simplified three-transistor structure to adapt to various display panel designs, including high-resolution and narrow-frame configurations, without compromising functionality.
Solution Approach 2:
The patent enables design flexibility by allowing the clock signal parameters (frequency, duty cycle) to be adjusted independently through the output sub-circuit. This parameter adjustability allows the same simplified circuit structure to accommodate different display resolutions and frame rates, expanding the design space for various display applications.
Data Source
AI summary
A shift register and a method for driving the same, a gate driving circuit and a display device. The shift register includes: an input sub-circuit configured to provide a signal at the signal input terminal to the pull-up node under control of the first clock signal terminal; an output sub-circuit configured to provide a clock signal at the second clock signal terminal to the signal output terminal under control of the pull-up node; and a pull-down sub-circuit configured to provide a signal at the power supply terminal to the signal output terminal under control of the third clock signal terminal.