Ga-Doped SiGe Epitaxial Source-Drain for FinFET Contact Resistance
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Solution Overview
Problem
In the manufacturing of semiconductor devices, particularly fin field effect transistors (FinFETs), there is a challenge in reducing contact resistance between source/drain regions and metal contacts due to thermal operations that decrease active carriers, affecting the electrical properties of p-type FETs.
Innovation Solution
Incorporating gallium (Ga) into the Ge-containing epitaxial layers of the source/drain regions with a high Ge concentration (60 mol % or more) to reduce lattice stress and contact resistance, while varying Ga concentration gradients within the epitaxial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thermal operations are performed to manufacture semiconductor devices, then device fabrication is enabled, but contact resistance between source/drain regions and metal contacts increases
Solution Approach 1:
The patent applies local quality by creating a Ga-doped region specifically at the contact interface between the source/drain epitaxial layer and metal contacts. The Ga concentration is highest at the outer surface adjacent to metal contacts and decreases toward the channel region, providing localized improvement of contact resistance without affecting other device regions. This selective doping addresses the contact resistance problem caused by thermal operations while preserving the electrical properties of the channel region.
Solution Approach 2:
The patent utilizes parameter changes by varying the Ga concentration as a gradient from the channel region toward the outer surface. The Ga concentration is controlled to be highest at the contact interface and decrease toward the channel, with the Ga amount being 1×10^18 to 1×10^22 atoms/cm³. This concentration gradient optimizes contact resistance reduction while managing lattice stress and maintaining device performance through controlled parameter variation.
2Reliability
If high Ge concentration (60 mol % or more) is used in epitaxial layers to reduce source/drain resistance, then electrical conductivity improves, but lattice stress increases
Solution Approach 1:
The patent applies local quality by concentrating Ga doping at the outer surface region adjacent to metal contacts while maintaining lower Ga concentration near the channel region. This localized approach allows the high Ge concentration (60 mol % or more) to be used throughout the source/drain epitaxial layer for low resistance, while Ga is strategically placed only where needed for contact resistance reduction and stress management, preventing excessive lattice stress in the channel region.
Solution Approach 2:
The patent creates a composite structure by combining Ge-containing semiconductor material with Ga doping. The source/drain epitaxial layer consists of Ge-containing material (60 mol % or more) that provides low resistance, while Ga is incorporated as a dopant element that modifies the electrical and mechanical properties at the contact interface. This composite approach allows simultaneous achievement of low source/drain resistance and controlled lattice stress through the synergistic effect of Ge and Ga.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The incorporation of Ga in the Ge-containing epitaxial layers reduces source/drain resistance by 10% to 30% and stabilizes electrical properties by releasing local lattice stress, improving contact resistance with metal layers.
Implementation Method 1
Incorporating gallium (Ga) into the Ge-containing epitaxial layers of the source/drain regions with a high Ge concentration (60 mol % or more) to reduce lattice stress
Implementation Method 2
sources and drains are formed by using an epitaxial growth method
Data Source
AI summary
A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1−x−yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.