Ga-Doped Source Drain Contacts in Ge Transistors
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Solution Overview
Problem
Transistors with high germanium content face challenges in achieving low contact resistance due to the low solubility of conventional dopants like boron, leading to higher contact resistance in Ge-based transistors.
Innovation Solution
The use of gallium (Ga) as a dopant in source and drain contacts, combined with a rapid annealing process to increase Ga concentration above its chemical stability limit, forming a crystalline Ga-doped layer with a homogeneous concentration greater than 5×10^20 atoms/cm^3, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If boron is used as a dopant in Ge-based transistors, then the doping process is simple and conventional, but the contact resistance increases due to low solubility of boron in high Ge content materials
Solution Approach 1:
The patent changes the dopant parameter from boron to gallium, which has significantly higher solubility in germanium (5.5×10^18 at./cm³ vs. 5.5×10^20 at./cm³). This parameter change allows achieving the required dopant concentration in Ge-based transistors without exceeding solubility limits, thereby reducing contact resistance while maintaining process feasibility
Solution Approach 2:
The patent creates a composite doping approach by combining gallium doping with rapid thermal annealing processes. The composite effect of Ga implantation followed by rapid annealing enables achieving homogeneous high concentration doping (greater than 5×10^20 at./cm³) that neither process could achieve alone, resolving the contradiction between ease of manufacture and contact resistance
2Reliability
If high concentration of dopant is introduced to reduce contact resistance, then contact resistance decreases, but precipitate formation occurs reducing material homogeneity
Solution Approach 1:
The patent changes the thermal processing parameters by implementing rapid thermal annealing with controlled temperature profiles. This parameter change allows introducing high concentrations of gallium (exceeding equilibrium solubility) while the rapid processing prevents precipitate formation, maintaining material homogeneity even at dopant concentrations greater than 5×10^20 at./cm³
Solution Approach 2:
The patent applies preliminary gallium ion implantation to introduce the dopant into the semiconductor structure before applying the rapid thermal annealing. This preliminary action ensures uniform distribution of Ga atoms throughout the target region, and the subsequent rapid annealing locks in this homogeneous distribution without allowing precipitate formation, thus achieving both low contact resistance and material stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly decreases contact resistance while maintaining a chemically homogeneous material, avoiding precipitate formation and enhancing electrical conductivity.
Implementation Method 1
implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer
Implementation Method 2
annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration
Data Source
AI summary
Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.


