GAA Gate Structure With Air Gaps for Easier High-k Patterning
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Solution Overview
Problem
The challenge in manufacturing small GAA devices is the difficulty in filling high-k metal gates in the vertically shrinking space between channels, requiring stringent process control for patterning, which is not fully satisfactory in existing semiconductor devices and methods.
Innovation Solution
A method that involves forming channels with increased widths from the bottom to the top, controlling the horizontal distance between the topmost channel and a nearby dummy fin to be smaller than twice the thickness of a hard mask layer, allowing the hard mask layer to be deposited only at the top of the topmost channel and between it and the dummy fin, thereby simplifying the patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the vertical space between channels is reduced to make smaller GAA devices, then device scaling is achieved, but the difficulty of filling high-k metal gates and controlling patterning increases
Solution Approach 1:
The patent transitions from vertical stacking of channels to a planar arrangement where channels are positioned horizontally adjacent to a dummy fin. This dimensional change allows high-k metal gate filling to occur in the horizontal plane rather than the vertical dimension, avoiding the crowding issues that arise when vertical space is reduced.
Solution Approach 2:
The dummy fin serves as an intermediary structure that facilitates the patterning process. By positioning channels adjacent to the dummy fin and controlling the horizontal distance between them, the patent creates a reference structure that simplifies the deposition and patterning of hard mask layers and high-k metal gates, reducing the stringency of process control requirements.
2Manufacturing precision
If tighter process control is implemented for patterning, then manufacturing precision is improved, but device complexity and process difficulty increase
Solution Approach 1:
The patent performs preliminary actions by forming the dummy fin structure and positioning channels at specific horizontal distances before the high-k metal gate deposition. This pre-establishment of geometric relationships creates built-in process margins that reduce the stringency of subsequent patterning steps, allowing for easier manufacturing while maintaining precision.
Solution Approach 2:
The patent changes the critical parameter from vertical spacing to horizontal distance control. By specifying that the horizontal distance between the topmost channel and dummy fin be smaller than twice the hard mask layer thickness, the patent transforms a difficult vertical filling problem into a more manageable horizontal dimensioning problem that is less sensitive to process variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the need for stringent process control, making the patterning of high-k metal gates easier and more efficient, avoiding the complexities and defects associated with tighter process control in existing methods.
Implementation Method 1
allowing the hard mask layer to be deposited only at the top of the topmost channel and between it and the dummy fin
Implementation Method 2
allowing the hard mask layer to be deposited only at the top of the topmost channel and between it and the dummy fin
Data Source
AI summary
A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.