GAA Field-Effect Transistor Air Spacer for Lower Parasitic Capacitance
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Solution Overview
Problem
Current materials are insufficient in reducing parasitic capacitance in advanced technology nodes of semiconductor devices, particularly in middle-end-of-line capacitance (CMEOL), which affects electronic device performance.
Innovation Solution
The introduction of an air spacer formed by a removable metal gate hard mask liner, which replaces traditional dielectric materials, reducing parasitic capacitance by incorporating air gaps in the gate-all-around (GAA) transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional dielectric materials are used in GAA transistor structures, then manufacturing is easier, but parasitic capacitance cannot be reduced sufficiently
Solution Approach 1:
The patent changes the dielectric constant parameter by replacing traditional dielectric materials with air spacers, reducing the dielectric constant from typical values (e.g., SiO2: 3.9) to approximately 1.0 for air, thereby reducing parasitic capacitance by up to 3% or more
Solution Approach 2:
The patent extracts the dielectric material from the spacer region and replaces it with air, creating air spacers between the gate structure and source/drain contacts. This removal of material achieves the desired capacitance reduction while the metal gate hard mask liner provides the necessary structural definition
2Reliability
If air spacers are introduced to reduce parasitic capacitance, then device performance improves, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the metal gate hard mask liner on the gate structure before forming the air spacers. This preliminary deposition creates a defined surface that guides subsequent spacer formation and ensures proper alignment, simplifying the overall process despite the introduction of air spacers
Solution Approach 2:
The metal gate hard mask liner serves as an intermediary element that facilitates the formation of air spacers. It provides a defined interface and structural support during the spacer formation process, making the complex air spacer integration more manageable
3Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases, but parasitic capacitance reduction becomes more difficult
Solution Approach 1:
The patent applies local quality by introducing air spacers specifically in the critical region between the gate structure and source/drain contacts, where parasitic capacitance has the greatest impact on device performance. This localized approach targets the most problematic areas without requiring global redesign of the entire transistor structure
Solution Approach 2:
The patent changes the dielectric parameter locally in the spacer region to reduce capacitance, maintaining the scaled-down geometry for high functional density while addressing parasitic capacitance in the specific region where it matters most for device performance
Data Source
AI summary
A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.