GAA Semiconductor Structure With Air Spacers to Reduce Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) devices face challenges as they scale down, leading to increased parasitic capacitance, which decreases performance.
Innovation Solution
Incorporating voids between the gate structure and contact etch stop layer as gate spacers to reduce parasitic capacitance, and employing a multi-patterning process to form GAA transistor structures, including the use of sacrificial layers and selective etching to create vertically stacked nanosheets or nanowires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GAA devices are scaled down using conventional manufacturing methods, then device density and integration are improved, but parasitic capacitance increases and performance decreases
Solution Approach 1:
The patent extracts the harmful dielectric material from the region between the gate structure and contact etch stop layer, replacing it with voids (air gaps). This removal of the dielectric material eliminates the source of parasitic capacitance while maintaining the structural integrity and electrical performance of the scaled-down GAA devices.
Solution Approach 2:
The patent introduces porous void structures between the gate and contact etch stop layer. These air-filled voids provide low dielectric constant regions that reduce parasitic capacitance, enabling continued scaling of GAA devices without the performance degradation caused by conventional filled structures.
2Area of stationary object
If gate-all-around structures are implemented to reduce chip footprint, then device integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions through multi-patterning processes that pre-establish the complex GAA structure geometry before final fabrication. By performing patterning steps in advance and using sacrificial layers to guide subsequent processing, the manufacturing complexity is managed systematically while achieving the desired gate-all-around configuration.
Solution Approach 2:
The patent uses sacrificial layers as intermediary structures during fabrication. These temporary structures facilitate the formation of complex GAA geometries and void patterns, and are subsequently removed to reveal the final structure. The sacrificial layers act as mediators that simplify the manufacturing process by breaking down complex steps into manageable sequential operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, enhancing the performance of GAA devices by improving gate control and scaling capability.
Implementation Method 1
utilizing air with a low dielectric constant to act as gate spacers, which reduces parasitic capacitance
Data Source
AI summary
A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.