GAA Anti-Fuse Structure With Dual Oxide for Easier Programming
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the constraints on lithographic processes used to pattern these features, leading to a trade-off between critical dimension and spacing.
Innovation Solution
The integration of a gate-all-around (GAA) device based anti-fuse structure with a dual oxide layer, where a thicker oxide is used in the anti-fuse region to facilitate sharper silicon channel edges, enabling easier programming and reducing the need for additional masks and processes, while allowing for the formation of one-time programmable circuits for security keys or memory redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional lithographic processes are used to pattern multi-gate and nanowire transistors at dimensions below 10 nanometer node, then device density increases, but manufacturing precision deteriorates due to trade-off between critical dimension and spacing
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D vertical stacking of nanowires. Multiple nanowires are stacked vertically to achieve higher device density without requiring further reduction of lateral critical dimensions. This vertical dimensionality change allows scaling while maintaining manufacturable lateral dimensions that current lithography can reliably pattern.
Solution Approach 2:
The transistor channel is segmented into multiple discrete nanowires stacked vertically, with each nanowire providing an independent conduction path. This segmentation allows the total channel width to be distributed across multiple smaller, more easily manufacturable features rather than requiring a single large-scale feature that pushes lithographic limits.
2Ease of operation
If thicker oxide is used in anti-fuse region, then programming ease improves with sharper silicon channel edges, but device complexity increases due to dual oxide structure
Solution Approach 1:
The patent implements different oxide thicknesses in different spatial regions: a thicker oxide layer in the anti-fuse region to enable sharper silicon channel edges and easier programming, and a thinner oxide layer in the transistor region to maintain proper device operation. This local differentiation of oxide quality allows each region to be optimized for its specific function.
Solution Approach 2:
The dual oxide structure acts as an intermediary solution between the conflicting requirements of programming ease (requiring thick oxide for sharp edges) and device operation (requiring thin oxide for proper electrical characteristics). Each oxide layer mediates the specific needs of its region, with the thicker oxide mediating the anti-fuse programming requirement and the thinner oxide mediating the transistor operational requirement.
Data Source
AI summary
Integrated circuit structures having anti-fuse structures, and methods of fabricating integrated circuit structures having anti-fuse structures, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A first gate structure is over the first vertical stack of horizontal nanowires, the first gate structure including a first gate dielectric and a first gate electrode completely surrounding a channel region of each nanowire of the first vertical stack of horizontal nanowires. The integrated circuit structure also includes a second vertical stack of horizontal nanowires. A second gate structure is over the second vertical stack of horizontal nanowires, the second gate structure including a second gate dielectric and a second gate electrode only partially surrounding a channel region of each nanowire of the second vertical stack of horizontal nanowires.