GAA APT Isolation Layout for Junction Leakage and Latch-Up
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Solution Overview
Problem
Conventional gate-all-around (GAA) devices face challenges such as junction leakage and latch-up issues between epitaxial source/drain features due to direct contact with the substrate, which degrade device performance.
Innovation Solution
Incorporation of an anti-punch through (APT) layer isolated from the substrate by a substrate isolation layer, with a higher dopant concentration than the substrate, and extending under the epitaxial S/D features, mitigating direct contact and using a bulk Si substrate for cost-effective isolation without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial source/drain features directly contact the substrate, then fabrication is simpler and cost is reduced, but junction leakage and latch-up issues occur degrading device performance
Solution Approach 1:
An anti-punch through (APT) layer is introduced as an intermediary between the substrate and epitaxial source/drain features. This APT layer extends under the epitaxial S/D features and is isolated from the substrate by a substrate isolation layer, preventing direct contact while maintaining fabrication compatibility and reducing junction leakage and latch-up issues
2Reliability
If substrate isolation layer is added to prevent junction leakage, then device performance improves, but fabrication cost and process complexity increase
Solution Approach 1:
The substrate isolation layer serves multiple functions: it isolates the APT layer from the substrate to prevent junction leakage, provides mechanical support, and enables cost-effective fabrication using bulk Si substrate without requiring additional specialized processing steps. The APT layer itself with higher dopant concentration also provides substrate isolation functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The APT layer effectively reduces junction leakage and latch-up issues, improving GAA device performance while maintaining compatibility with existing fabrication processes and reducing fabrication costs.
Implementation Method 1
An anti-punch through (APT) layer is formed between the substrate and epitaxial source/drain features, isolated by a dielectric material, with a higher dopant concentration than the substrate
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.