Gate-All-Around Nanosheet Structure With APT Layer for Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges in controlling leakage current in semiconductor layers not fully surrounded by a gate, such as the layer below the bottommost nanosheet or nanowire, which affects power consumption and device performance.
Innovation Solution
The introduction of an anti-punch-through (APT) doping layer in the semiconductor layer to reduce leakage current, combined with proper biasing of source, drain, and well terminals, and the use of low resistance metal compositions for contact and via structures to minimize IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around devices are used to improve gate control and reduce short-channel effects, then gate-channel coupling is increased, but leakage current in semiconductor layers not fully surrounded by gate cannot be controlled
Solution Approach 1:
The patent introduces an anti-punch-through (APT) doping layer with specific doping concentration in the semiconductor layer below the bottommost nanosheet or nanowire. This creates a localized doped region that specifically addresses the leakage current issue in the partially-gated semiconductor layer without affecting the overall GAA device structure or the fully-gated channel regions.
Solution Approach 2:
The APT doping layer is formed before the final device assembly, pre-establishing the doped region that will suppress leakage current. This preliminary doping action ensures that when the device operates, the leakage suppression is already in place, preventing harmful effects rather than correcting them later.
2Object-generated harmful factors
If doping is increased to suppress leakage current, then leakage current is reduced, but dopant diffusion into channel layers increases
Solution Approach 1:
The APT doping layer is positioned specifically in the semiconductor layer below the bottommost nanosheet or nanowire, creating a localized doped region. This spatial localization ensures that dopants are concentrated where needed for leakage suppression while minimizing diffusion into the fully-gated channel layers, thus resolving the contradiction between leakage suppression and dopant diffusion control.
Solution Approach 2:
The APT doping layer acts as an intermediary structure between the substrate and the channel layers. It provides a controlled doping region that mediates the electrical properties to suppress leakage current while the gate structure and other design elements work together to prevent excessive dopant diffusion into sensitive channel regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The APT doping layer effectively suppresses leakage current while minimizing dopant diffusion into channel layers, thereby reducing power consumption and enhancing device performance, particularly in standby modes.
Implementation Method 1
The introduction of an anti-punch-through (APT) doping layer in the semiconductor layer to reduce leakage current
Implementation Method 2
the use of low resistance metal compositions for contact and via structures to minimize IR drop
Data Source
AI summary
A semiconductor device includes a substrate, a p-type well over the substrate and having a p-type anti-punch-through (APT) layer, an n-type source feature and an n-type drain feature over the p-type APT layer, and multiple first channel layers suspended over the p-type APT layer and connecting the n-type source feature to the n-type drain feature. The multiple first channel layers are vertically stacked one over another and are undoped. The semiconductor device further includes a high-k metal gate wrapping around each of the first channel layers, a first source contact disposed over and electrically coupled to the n-type source feature, and a drain contact disposed over and electrically coupled to the n-type drain feature. A bottom surface of the n-type source feature is about 5 nm to about 25 nm below an interface between the high-k metal gate and the p-type APT layer.