GAA Transistor Backside Contact Isolation to Reduce Leakage
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Solution Overview
Problem
The semiconductor manufacturing process becomes increasingly complex as IC dimensions are reduced, necessitating improvements in manufacturing processes to maintain low cost, high performance, and low power consumption in integrated circuits.
Innovation Solution
A gate all around (GAA) transistor structure is patterned using photolithography and self-aligned processes, incorporating epitaxial bottom isolation structures with improved semiconductor layers and dielectric spacers to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dimensions are reduced to increase production efficiency and reduce costs, then productivity improves, but device complexity increases
Solution Approach 1:
The substrate is divided into active regions and isolation regions, with the isolation region further segmented into multiple dielectric layers (first dielectric layer, second dielectric layer) and epitaxial structures. This segmentation allows for better control of electrical isolation and reduced parasitic effects, enabling scaled dimensions while managing process complexity through modular structure design.
Solution Approach 2:
Different regions of the device are given different properties: the isolation region contains epitaxial structures with specific doping profiles and multiple dielectric layers with different materials and thicknesses, while active regions maintain different semiconductor materials (e.g., SiGe source/drain vs. Si channel). This local differentiation optimizes performance for each region's specific function while allowing overall device scaling.
2Reliability
If epitaxial structures are formed in isolation regions to reduce parasitic effects, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The epitaxial structure in the isolation region is designed asymmetrically with respect to the surrounding structure. The first and second dielectric layers have different thicknesses and materials, and the epitaxial structure extends differently relative to the active region boundaries. This asymmetric design provides optimized electrical isolation and reduced parasitic effects without requiring symmetric complexity throughout the entire device structure.
Solution Approach 2:
The epitaxial structure is nested within the isolation region, which itself is surrounded by active regions. Multiple dielectric layers are nested within the epitaxial structure, creating a hierarchical nesting arrangement. This nesting approach consolidates multiple isolation functions into a compact structure, reducing the overall footprint and managing complexity through nested organization rather than distributed elements.
Data Source
AI summary
A semiconductor device including a first epitaxial source/drain feature, a second epitaxial source/drain feature, two or more semiconductor layers electrically connected to the first and second epitaxial source/drain features, a backside source/drain contact, and a bottom dielectric layer is provided. The backside source/drain contact is disposed on one side of the first epitaxial source/drain feature, the backside source/drain contact is electrically connected to a bottom surface of the first epitaxial source/drain feature. The bottom dielectric layer is disposed on a backside of the semiconductor layers, and the bottom dielectric layer electrically isolates the backside source/drain contact from the semiconductor layers.