GAA Backside Contact Layout for Lower Source-Drain Resistance
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to reduce contact resistance while maintaining mobility improvement and short channel control, particularly in multi-gate transistors, without incurring capacitive coupling penalties, as conventional processes face limitations in lithographic processes and spacing constraints.
Innovation Solution
The implementation of a self-aligned backside contact process with enhanced area relative to epitaxial source or drain regions, utilizing etches to create a reentrant profile and a protective helmet layer to form a widened trench for conductive contact, ensuring reduced contact resistance without capacitive coupling penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithographic processes are used to pattern semiconductor features, then manufacturing precision is maintained, but spacing between features cannot be reduced sufficiently to increase device density
Solution Approach 1:
The patent introduces self-aligned backside contact formation that utilizes the vertical dimension and backside access to create contact openings. By forming contacts from the backside of the substrate and using self-alignment techniques, the process bypasses conventional lithographic spacing constraints on the front side, enabling tighter effective spacing and increased device density without compromising manufacturing precision.
2Manufacturing precision
If contact area is reduced to maintain lithographic spacing, then spacing constraints are satisfied, but contact resistance increases
Solution Approach 1:
The patent inverts the conventional approach by forming contact openings from the backside of the substrate rather than from the front side. This inversion allows contact areas to be enlarged without encroaching on front-side feature spacing, thereby maintaining manufacturing precision while reducing contact resistance through increased contact area.
Solution Approach 2:
By utilizing the backside dimension of the substrate, the patent creates additional space for enlarged contact areas. This dimensional approach allows contacts to be expanded in the vertical and backside horizontal dimensions without affecting front-side feature spacing, thus reducing contact resistance while maintaining spacing requirements.
3Productivity
If multi-gate transistor dimensions are scaled down to increase device density, then device capacity increases, but short channel control and mobility improvement become difficult to maintain
Solution Approach 1:
The patent segments the transistor structure into multi-gate configurations where the gate surrounds the channel from multiple directions. This segmentation of the gate structure provides enhanced electrostatic control over the channel, maintaining short channel control and mobility improvement even as device dimensions are scaled down to increase density.
Data Source
AI summary
Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.