GAA Backside Contact Structure for Lower Parasitic Resistance
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving higher device density, performance, and lower costs as they transition to nanometer technology process nodes, particularly in the design and fabrication of three-dimensional structures.
Innovation Solution
The development of gate all around (GAA) transistor structures, which involve forming a fin structure with alternately stacked semiconductor layers, patterning via self-aligned processes, and forming conductive vias to reduce parasitic resistance and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor structures are used, then manufacturing process is simple, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to three-dimensional gate-all-around (GAA) structures with vertically stacked channels. This dimensional change enables multiple active channels per footprint area, dramatically increasing device density while maintaining manufacturability through adapted fabrication processes
2Productivity
If device dimensions are reduced to nanometer nodes, then device density increases, but fabrication challenges and performance variability worsen
Solution Approach 1:
The device structure is segmented into multiple discrete layers (semiconductor layers, dielectric layers, conductive layers) that are sequentially formed and patterned. This segmentation allows independent control and optimization of each layer's thickness and properties, improving manufacturing precision at nanometer nodes while enabling higher device density
3Reliability
If parasitic resistance is reduced through via formation, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
Conductive vias and contact structures are formed at strategic locations during the fabrication sequence before final interconnect assembly. This preliminary action establishes low-resistance current paths early in the process, reducing parasitic resistance and improving device performance while managing manufacturing complexity through integrated process flow
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and the fin structure includes a plurality of nanostructures stacked in a vertical direction. The semiconductor device structure includes a gate structure formed over the fin structure, and an S/D structure formed adjacent to the gate structure. The semiconductor device structure includes a first via formed adjacent to the S/D structure, and a first contact structure formed over the S/D structure. The semiconductor device structure includes a second contact structure formed below the S/D structure, and the first via is in direct contact with the first contact structure and the second contact structure.