GAA Transistor Backside Contacts With Two-Step Etch-Back

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Solution Overview

Problem

Integration of gate-all-around (GAA) transistor features in semiconductor fabrication is challenging, requiring improved methods to enhance gate control, reduce OFF-state current, and minimize short-channel effects.

Innovation Solution

A method involving double-patterning or multi-patterning processes to form GAA structures, including a two-step etching back process for forming back-side source/drain contact structures, and a bottom-up deposition process to minimize resistance and prevent defects, combined with the use of high-k dielectric layers and metal gate electrodes to enhance gate control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional single-patterning methods are used to form GAA structures, then the fabrication process is simpler, but the gate control and short-channel effects are not sufficiently improved

Engineering Contradiction:
Improvegate control precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is divided into multiple patterning steps (double-patterning or multi-patterning) to achieve precise GAA structure formation. This segmentation allows for better control of the gate-all-around features around the nanowire channel, improving gate control precision while managing the complexity through systematic process breakdown

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate structure is extended to surround the channel region in multiple dimensions (gate-all-around configuration), providing access to the channel on two or four sides. This dimensional approach enhances gate control and reduces short-channel effects by increasing gate-channel coupling from a single-plane to a multi-dimensional configuration

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If standard deposition processes are used for back-side source/drain contact structures, then the process is faster, but resistance is higher and defects occur

Engineering Contradiction:
Improvecontact structure reliabilityVSAvoidfabrication efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

A liner layer is introduced as an intermediary between the substrate and the conductive materials in the back-side source/drain contact structures. This liner layer prevents direct contact that would cause defects and enables the bottom-up deposition process to proceed effectively, improving contact structure reliability while maintaining fabrication efficiency

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The liner layer is formed in advance before depositing the conductive materials, preparing the surface for bottom-up deposition. This preliminary action prevents defects during subsequent deposition steps and ensures low-resistance contact structures are formed efficiently

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method facilitates the formation of GAA transistors with improved gate control and reduced resistance, addressing integration challenges and enhancing performance.

Implementation Method 1

forming a back-side source/drain contact structure by a two-step etching back process

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

depositing a first conductive material over the second silicide layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 3

depositing a second conductive layer in the trench

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS12408394B2Semiconductor device structure and method for forming the same
Publication Date: 2025.09.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12408394B2 patent drawing
  • US12408394B2 patent drawing
  • US12408394B2 patent drawing

AI summary

A method for forming a semiconductor device structure includes forming nanostructures over a front side of a substrate. The method also includes forming a gate structure surrounding the nanostructures. The method also includes forming a source/drain structure beside the gate structure. The method also includes forming a trench though the substrate from a back side of the substrate. The method also includes forming a first silicide layer in contact with the source/drain structure. The method also includes forming a second silicide layer over the first silicide layer and the sidewalls of the trench. The method also includes depositing a first conductive material over the second silicide layer. The method also includes etching back the first conductive material. The method also includes etching back the second silicide layer. The method also includes depositing a second conductive material in the trench.