GAA Capacitor Structure Using Series Devices for Higher Withstand Voltage
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Solution Overview
Problem
Current gate-all-around (GAA) processes are inadequate for fabricating capacitors for high-voltage applications, as they are limited to lower withstand voltages, making it challenging to support devices operating between 1.2 and 2.5V, which is necessary for advanced integrated circuit (IC) devices.
Innovation Solution
A semiconductor structure is developed that includes multiple gate-all-around field-effect transistor devices connected in series, with dielectric layers forming capacitors, allowing for increased voltage rating by connecting multiple core device capacitors in series, thereby enhancing the withstand voltage for input/output devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If standard gate-all-around (GAA) processes are used, then device scaling and power performance are improved, but withstand voltage is limited to low-voltage applications
Solution Approach 1:
The patent divides a single high-voltage capacitor into multiple lower-voltage capacitors connected in series. Each capacitor is formed using a separate GAA core device with its own gate structure and epitaxial source/drain features. By segmenting the voltage requirement across multiple devices, the structure achieves high withstand voltage capability while maintaining compatibility with low-voltage GAA fabrication processes.
Solution Approach 2:
The patent embeds multiple capacitor structures within a shared trench infrastructure. Multiple gate structures and epitaxial source/drain feature sets are nested within the same trench, sharing common isolation dielectric material and trench boundaries. This nested arrangement allows multiple capacitors to occupy overlapping spatial regions, reducing overall footprint while achieving the required series voltage rating.
2Reliability
If multiple capacitors are connected in series to increase voltage rating, then withstand voltage is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple capacitor structures into a unified trench-based architecture. Multiple gate structures are positioned within a single trench, sharing common isolation dielectric material and trench boundaries. The epitaxial source/drain features of adjacent capacitors are electrically connected through shared regions, reducing the need for separate interconnect structures. This merging approach reduces overall structural complexity compared to implementing each capacitor as a separate discrete device.
Solution Approach 2:
The patent designs the trench structure to serve multiple functions simultaneously: it provides mechanical support, electrical isolation through dielectric material, and defines the boundaries for multiple nested capacitor structures. The isolation dielectric material serves both as an insulator between capacitors and as a structural element filling the trench space. This multi-functionality reduces the number of separate components needed, simplifying the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the creation of capacitors with higher voltage ratings, addressing the limitations of existing GAA processes by allowing capacitors to operate effectively at higher voltages, thus supporting advanced IC devices with improved power handling capabilities.
Implementation Method 1
The gate structure and the epitaxial source/drain features and a portion of the isolation dielectric material between the gate structure and the epitaxial source/drain features form a capacitor
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, first and second well regions, first and second gate-all-around (GAA) field-effect transistor devices and a first dielectric layer. The first and second well regions are arranged in the semiconductor substrate and separated from each other. Top and bottom surfaces of the first and second well regions are aligned with top and bottom surfaces of the semiconductor substrate. The first and second GAA field-effect transistor devices are formed over the first and second well regions. A first gate structure of the first GAA field-effect transistor device is electrically connected to a power supply terminal. The first epitaxial source/drain features of the first GAA field-effect transistor are electrically connected to the second gate structure of the second GAA field-effect transistor. The second epitaxial source/drain features of the second GAA field-effect transistor are electrically connected to a ground terminal.