GAA Circuit Cell Layout With Variable Nanosheet Dimensions
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Solution Overview
Problem
Existing technologies for fabricating gate-all-around (GAA) transistors in integrated circuits have not been entirely satisfactory in all respects, particularly in terms of complexity and efficiency during scaling down processes.
Innovation Solution
The fabrication of GAA transistors involves patterning methods such as photolithography and self-aligned processes, allowing for the creation of transistors with varying channel widths and thicknesses, including double-patterning or multi-patterning techniques to achieve smaller pitches, and the use of sacrificial layers to form spacers for GAA structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and self-aligned processes are used to pattern GAA transistors, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the transistor fabrication into distinct stages: forming sacrificial layers at specific positions, depositing spacer material, and selectively removing sacrificial layers. This multi-step self-aligned process segments the complex patterning task into manageable steps, each achieving a specific geometric outcome with high precision while managing overall process complexity
Solution Approach 2:
The patent employs preliminary action through self-aligned processes where sacrificial layers are deposited and patterned before the actual transistor structures are formed. The spacers are formed in advance using these sacrificial layers as templates, ensuring precise alignment is achieved before final transistor fabrication begins
2Productivity
If scaling down is implemented to increase functional density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the thickness of sacrificial layers and spacer materials to achieve different transistor geometries. By controlling the thickness parameters of deposited layers through atomic layer deposition (ALD), the process achieves high precision geometric control at scaled dimensions while maintaining productivity through standardized deposition parameters
3Reliability
If gate-all-around structures are formed to improve gate control, then transistor performance is improved, but device complexity increases
Solution Approach 1:
The patent applies the nested doll principle by forming gate structures that completely surround the channel region in three dimensions. The gate electrode and gate dielectric are nested around the semiconductor channel from all sides, creating a gate-all-around structure that provides maximum gate control through complete spatial enclosure of the channel
4Manufacturing precision
If multi-patterning techniques are used to achieve smaller pitches, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent applies self-service through self-aligned processes where previously deposited structures automatically serve as alignment references for subsequent steps. The spacers form self-aligned to the sacrificial layers, and subsequent transistor structures align to the spacers, eliminating the need for additional photolithography alignment steps and reducing overall fabrication time while achieving small pitches
Data Source
AI summary
A semiconductor device includes a first circuit cell having first transistors, and a second circuit cell having second transistors and arranged with the first circuit cell in an X-direction. Each of the first transistors includes first nanostructures vertically stacked from each other. Each of the second transistors includes second nanostructures vertically stacked from each other. A cell pitch of the first circuit cell and a cell pitch of the second circuit cell in a Y-direction are the same. A first pitch of the first nanostructures in the Z-direction and a second pitch of the second nanostructures in the Z-direction are the same. A first thickness of the first nanostructures in the Z-direction is greater than a second thickness of the second nanostructures in the Z-direction. A first width of the first nanostructures in the Y-direction is greater than a second width of the second nanostructures in the Y-direction.