Gate-All-Around Channel Layout for Larger Source/Drain Contact Area

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Solution Overview

Problem

The scaling down of integrated circuits (ICs) leads to increased complexity and power dissipation, which is exacerbated by smaller contact areas between source/drain contacts and epitaxial source/drain regions, resulting in worse device performance and reduced yield due to potential bridging between adjacent epitaxial regions.

Innovation Solution

The formation of an epitaxial source/drain region with a square bar cross-sectional profile on a <110> channel over a (110) orientation substrate, providing a larger metal contact area and reducing the epitaxial source/drain region to prevent bridging and improve device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the geometry size is scaled down to increase functional density, then production efficiency is improved and costs are lowered, but power dissipation increases and device performance deteriorates

Engineering Contradiction:
Improveproduction efficiencyVSAvoidpower dissipation
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent changes the crystallographic orientation parameter of the substrate from conventional <100> to <110>, which fundamentally alters the material properties and carrier mobility characteristics. This parameter change enables achieving both high functional density and low power dissipation by exploiting the unique electronic structure of <110> oriented silicon, where carriers exhibit higher mobility along certain directions, thereby reducing resistive losses while maintaining scaling benefits

Inventive Principle:
Principle #35Parameter changes

2Volume of moving object

If the contact area between source/drain contacts and epitaxial source/drain regions is reduced due to scaling, then device size is decreased, but device performance worsens

Engineering Contradiction:
Improvedevice sizeVSAvoiddevice performance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating a non-uniform contact geometry where the epitaxial source/drain region forms a square bar profile with enhanced contact footprint at the metal-semiconductor interface. This localized geometric optimization ensures sufficient contact area for reliable electrical connection while maintaining overall device miniaturization, as the improved contact quality is confined to specific regions rather than requiring uniform enlargement throughout the device structure

Inventive Principle:
Principle #3Local quality

3Reliability

If the epitaxial source/drain region size is increased to improve contact area, then device performance improves, but bridging between adjacent epitaxial regions occurs

Engineering Contradiction:
Improvedevice performanceVSAvoidbridging prevention
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent employs asymmetry by designing the epitaxial source/drain region with a distinctive square bar cross-sectional profile that is wider in the lateral direction (parallel to substrate surface) than in the vertical direction. This asymmetric geometry provides sufficient lateral contact area for good electrical connection while limiting vertical and lateral expansion that could cause bridging to adjacent regions, thus simultaneously achieving reliable contact and preventing manufacturing defects

Inventive Principle:
Principle #4Asymmetry

4Manufacturing precision

If the process window is narrowed due to scaling challenges, then manufacturing precision requirements increase, but yield decreases

Engineering Contradiction:
Improveprocess controlVSAvoidyield
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent utilizes parameter changes by selecting <110> oriented substrate which inherently provides more tolerant epitaxial growth characteristics compared to conventional orientations. This parameter selection broadens the process window for epitaxial source/drain formation, allowing greater variation in process conditions (temperature, pressure, gas flow) while maintaining acceptable film quality, thereby reducing the stringency of manufacturing precision requirements and improving overall yield

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances device resistance, reduces the source/drain region merge window, and increases the process window, thereby improving overall device performance and yield.

Implementation Method 1

The formation of an epitaxial source/drain region with a square bar cross-sectional profile on a <110> channel over a (110) orientation substrate

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20230420506A1Semiconductor device and manufacturing method thereof
Publication Date: 2023.12.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230420506A1 patent drawing
  • US20230420506A1 patent drawing
  • US20230420506A1 patent drawing

AI summary

A method includes forming a channel region above a (110)-orientated substrate and having a length extending in a &lt;100&gt; direction; epitaxial growing a plurality of source/drain regions on either side the channel region; forming a gate structure surrounding the channel region; forming a plurality of source/drain contacts on the source/drain regions.