Gate-All-Around Channel Structure for Short-Channel Current Control
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling and improving performance and reliability, particularly in managing short channel effects and current control without increasing gate length, which are limitations in multi-gate transistors.
Innovation Solution
The semiconductor device incorporates a multi-channel active pattern with sheet patterns and a gate structure featuring an interfacial insulating film with varying dimensions and elemental concentrations, enhancing current control and reducing leakage current by strategically positioning the interfacial insulating film and source/drain patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistor structure is used, then current control ability is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate, second gate, third gate, fourth gate) arranged around the channel in a FinFET configuration. This segmentation allows independent control of different channel regions, improving current control ability while managing complexity through modular gate design
Solution Approach 2:
The transistor transitions from a planar 2D channel to a 3D FinFET structure with the channel extending vertically. The gate wraps around the channel in multiple dimensions, providing superior electrostatic control and current modulation without proportionally increasing device footprint complexity
2Reliability
If gate length is increased to suppress short channel effects, then reliability is improved, but device scaling is hindered
Solution Approach 1:
The channel is extended vertically to form a fin structure, transitioning from 2D to 3D geometry. This vertical extension provides increased gate control over the channel without increasing the horizontal gate length, enabling effective short channel effect suppression while maintaining compact device footprint for continued scaling
Solution Approach 2:
Multiple gates are nested around the vertical channel fin structure, with gates positioned at different heights and orientations. This nested configuration maximizes gate control over the channel in three dimensions, providing superior short channel effect suppression without requiring increased gate length
3Reliability
If interfacial insulating film with higher first element concentration is placed near source/drain, then leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The interfacial insulating film exhibits spatially varying composition with higher first element concentration in the first region (near source/drain) and lower concentration in the second region (toward gate). This local quality variation reduces leakage current at critical interfaces while maintaining overall film functionality, achieved through selective deposition or annealing processes
Data Source
AI summary
A semiconductor device includes an active pattern including: a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; a gate structure on the lower pattern and including a gate electrode and a gate insulating film including an interfacial insulating film including a first vertical portion and a horizontal portion. A dimension in a third direction of the first vertical portion is greater than a dimension in the second direction of the horizontal portion. The first vertical portion includes: a first area contacting a source/drain pattern; and a second area provided between the first area and the gate electrode. The interfacial insulating film includes a first element other than silicon, wherein a concentration of the first element in the first area is greater than a concentration of the first element in the second area.