GAA MOSFET Channel Structure for Epitaxy and Gate Formation Margin
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Solution Overview
Problem
Conventional gate-all-around (GAA) transistor fabrication methods face challenges such as poor epitaxial growth in the source/drain region and limited formation margin for gate dielectric and electrodes in narrow channel spaces, affecting the performance and reliability of GAA devices.
Innovation Solution
The method involves forming semiconductor layers with varying thicknesses and widths to optimize epitaxial source/drain growth, using selective etching and partial etching treatments to create suitable regions for gate dielectric and metal gate formation, and employing high-k dielectric layers to improve gate control and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GAA device fabrication methods are used, then gate control is improved through gate-all-around structure, but epitaxial growth in source/drain region deteriorates and formation margin for gate dielectric and electrode becomes small
Solution Approach 1:
The patent applies local quality by creating different thickness regions within the semiconductor layer: a first thickness in the channel region and a second thickness (greater than the first) in the source/drain region. This allows the channel region to maintain thin dimensions for good gate control while the source/drain regions have increased thickness to provide adequate space for epitaxial growth and formation of gate dielectric and electrode layers without compromising manufacturing precision.
Solution Approach 2:
The semiconductor layer is segmented into distinct regions with different thickness characteristics: a channel region with first thickness and source/drain regions with second thickness. This segmentation enables independent optimization of each region's properties, allowing the channel to be thin for gate control while source/drain areas are thicker for manufacturing purposes.
2Reliability
If conventional GAA device fabrication methods are used, then gate control is improved through gate-all-around structure, but formation margin for gate dielectric and electrode in narrow channel spaces becomes small
Solution Approach 1:
The patent applies local quality by creating different thickness regions within the semiconductor layer: a first thickness in the channel region and a second thickness (greater than the first) in the source/drain region. This allows the channel region to maintain thin dimensions for good gate control while the source/drain regions have increased thickness to provide adequate space for epitaxial growth and formation of gate dielectric and electrode layers without compromising manufacturing precision.
Solution Approach 2:
The patent employs preliminary action by forming the semiconductor layer with non-uniform thickness before subsequent processing steps. The source/drain regions are pre-formed with greater thickness to anticipate and accommodate the space requirements for epitaxial growth and gate dielectric/electrode formation, ensuring adequate formation margin is available when these structures are later created.
3Productivity
If conventional GAA device fabrication methods are used, then device scaling is enabled, but process margins for gate dielectric and metal layer formation become limited
Solution Approach 1:
The patent applies local quality by creating different thickness regions within the semiconductor layer: a first thickness in the channel region and a second thickness (greater than the first) in the source/drain region. This allows the channel region to maintain thin dimensions for good gate control while the source/drain regions have increased thickness to provide adequate space for epitaxial growth and formation of gate dielectric and electrode layers without compromising manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality and reliability of GAA devices by allowing larger process margins for gate dielectric and metal layer formation, reducing voids and defects, and improving epitaxial source/drain feature growth, leading to better performance and functionality.
Implementation Method 1
employing high-k dielectric layers to improve gate control and reduce defects
Implementation Method 2
using selective etching and partial etching treatments to create suitable regions for gate dielectric and metal gate formation
Implementation Method 3
optimize epitaxial source/drain growth
Data Source
AI summary
The present disclosure provides an integrated circuit device that comprises a semiconductor substrate having a top surface; a first and a second source/drain features over the semiconductor substrate; a first semiconductor layer extending in parallel with the top surface and connecting the first and the second source/drain features, the first semiconductor layer having a center portion and two end portions, each of the two end portions connecting the center portion and one of the first and second source/drain features; a first spacer over the two end portions of the first semiconductor layer; a second spacer vertically between the two end portions of the first semiconductor layer and the top surface; and a gate electrode wrapping around and engaging the center portion of the first semiconductor layer. The center portion has a thickness smaller than the two end portions.