GAA Channel Release Structure for Uniform Inner Spacer Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GAA transistor fabrication technologies face issues such as excessive impurity diffusion, increased built-in stress, undesired capacitance, and device degradation due to scaling down, leading to non-uniformity and performance variability.
Innovation Solution
A method involving the formation of intermixing layers with lower germanium concentration between sacrificial and channel layers, followed by selective etching and deposition of dielectric and inner spacer layers to maintain channel member flatness and integrity, using processes like ALD and cross-linking treatments to ensure precise etching and gap filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GAA devices are scaled down to increase functional density, then production efficiency is improved and costs are lowered, but excessive impurity diffusion, increased built-in stress, undesired capacitance, and device degradation occur
Solution Approach 1:
The patent introduces intermixing layers with graded germanium concentration between channel layers and sacrificial layers. The germanium concentration varies locally from 0% to 30%, creating a gradient structure that provides different properties at different locations. This local quality variation reduces impurity diffusion and built-in stress while maintaining device performance during scaling.
Solution Approach 2:
The patent changes the germanium concentration parameter in the intermixing layers to optimize device performance. By adjusting the germanium concentration from 0% to 30% in a graded manner, the patent reduces impurity diffusion and built-in stress, thereby maintaining reliability as devices are scaled down for higher productivity.
2Ease of manufacture
If existing fabrication technologies are used for GAA transistors, then manufacturing process is simplified, but non-uniformity and performance variability increase
Solution Approach 1:
The patent performs preliminary actions by forming intermixing layers with graded germanium concentration before the main fabrication steps. This preliminary structuring prevents impurity diffusion and stress accumulation during subsequent processing, ensuring uniform channel members and reducing performance variability without significantly complicating the overall manufacturing process.
Solution Approach 2:
The patent uses composite structures with multiple layers having different germanium concentrations (0%, 10%, 20%, 30%). This composite approach creates a graded intermixing layer that maintains manufacturing feasibility while achieving superior uniformity and reducing performance variability in the final device.
3Ease of manufacture
If germanium-containing sacrificial layers are used, then selective etching is enabled, but impurity diffusion into channel layers occurs
Solution Approach 1:
The patent introduces intermixing layers as intermediary structures between the channel layers and germanium-containing sacrificial layers. These intermixing layers act as diffusion barriers that prevent germanium impurities from the sacrificial layers from diffusing into the channel layers, while still allowing selective etching to proceed. The graded germanium concentration (0% to 30%) in the intermixing layers provides this protective function.
Solution Approach 2:
The intermixing layers have locally varying germanium concentrations (0%, 10%, 20%, 30%) that create a gradient structure. The regions with lower germanium concentration near the channel layers provide better diffusion barrier properties, while regions with higher germanium concentration maintain etch selectivity. This local quality variation resolves the contradiction between selective etching capability and channel layer purity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures uniformity and stability of GAA transistor structures by maintaining channel member flatness and reducing etching loss, enhancing device performance and reliability.
Implementation Method 1
depositing a dielectric dummy layer around each of the channel members and over the source/drain trenches; depositing an inner spacer layer over the inner spacer recesses
Implementation Method 2
performing a cross-linking treatment on the dielectric dummy layer, such that the space is fully filled by the dielectric dummy layer
Implementation Method 3
selectively removing the sacrificial layers in the channel region to release the channel layers as channel members
Implementation Method 4
forming intermixing layers with lower germanium concentration between sacrificial and channel layers
Data Source
AI summary
A method of the present disclosure includes forming a stack that includes channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack over a channel region of the fin-shaped structure, recessing a source/drain region of the fin-shaped structure to form a trench, removing the sacrificial layers in the channel region to release the channel layers as channel members, partially filling a space vertically stacked between adjacent two of the channel members with a dielectric dummy layer, performing a treatment to expand the dielectric dummy layer to fully fill the space, laterally recessing the dielectric dummy layer to form recesses, forming inner spacers in the recesses, forming a source/drain feature in the trench, removing the dummy gate stack, removing the dielectric dummy layer to release the channel members, and forming a gate structure to wrap around the channel members.