Gate-All-Around Channel Structure With Interdiffusion Removal
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Solution Overview
Problem
Existing multi-gate device fabrication techniques, particularly for gate-all-around transistors, face challenges due to interdiffusion regions formed during the channel release process, which affect the performance and uniformity of the semiconductor devices.
Innovation Solution
A method involving selective and partial recessing of sacrificial layers to form inner spacer recesses, followed by additional etching processes to remove interdiffusion regions and modify the channel member dimensions, improving the uniformity and performance of gate-all-around transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate device fabrication is performed using existing techniques, then gate-all-around transistor structures can be formed, but interdiffusion regions are created that degrade device performance and uniformity
Solution Approach 1:
The patent applies preliminary action by performing selective recessing of sacrificial layers before complete channel release, creating inner spacer recesses that prevent interdiffusion regions from forming in the first place. This proactive measure eliminates the harmful effect before it can degrade device performance.
Solution Approach 2:
The patent extracts and removes the harmful interdiffusion regions through selective etching processes. By targeting and removing only the interdiffusion portions while preserving the main channel members, the patent eliminates the source of performance degradation and non-uniformity.
2Reliability
If additional etching processes are performed to remove interdiffusion regions, then device performance improves, but fabrication complexity increases
Solution Approach 1:
The patent applies local quality by performing etching operations that are highly selective in space and target. Instead of uniform etching across the entire structure, the process selectively removes interdiffusion regions at specific locations while leaving the main channel members intact. This localized approach improves performance without requiring complete restructuring of the fabrication process.
Solution Approach 2:
The patent uses inner spacers as intermediary structures that facilitate the removal of interdiffusion regions. These spacers serve as placeholders and etch stop layers, enabling selective removal of harmful regions while protecting the main channel members. The intermediary structures make the complex selective etching process controllable and manufacturable.
3Manufacturing precision
If selective recessing of sacrificial layers is performed, then inner spacer recesses are formed that improve uniformity, but process steps are added
Solution Approach 1:
The patent merges multiple functions into the selective recessing step. The same process that creates inner spacer recesses also serves as a preliminary etch stop mechanism and defines the boundaries for subsequent interdiffusion region removal. By combining these functions, the patent reduces the net increase in process complexity while achieving improved uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the performance of gate-all-around transistors by removing interdiffusion regions, ensuring uniform channel member dimensions and smoother surfaces, thereby improving the overall functionality of the semiconductor devices.
Implementation Method 1
performing an etching process to remove the interdiffusion region from the channel member
Data Source
AI summary
A method includes forming a fin-shaped structure disposed over a substrate, the fin-shaped structure including a stack of alternating channel layers and sacrificial layers, forming a dummy gate structure over a channel region of the fin-shaped structure, forming a source/drain recess in a source/drain region of the fin-shaped structure, selectively and partially recessing the sacrificial layers to form inner spacer recesses among the channel layers, forming inner spacer features in the inner spacer recesses, forming a source/drain feature in the source/drain recess, removing the dummy gate structure to form a gate trench, selectively removing the sacrificial layers to form an opening, performing an etching process to remove a portion of the channel layers and a portion of the inner spacer features, thereby enlarging the gate trench and the opening, and forming a gate structure in the enlarged gate trench and the enlarged opening.