Semiconductor Nanostructure Formation with Multi-Patterned GAA Channels
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with processing and manufacturing complexity.
Innovation Solution
The process involves forming FinFET structures and gate all around (GAA) transistor structures using double-patterning or multi-patterning techniques, which allow for the creation of patterns with smaller pitches than traditional photolithography, involving sacrificial layers, spacers, and epitaxial growth to achieve precise and reliable device formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography is used for patterning, then the fabrication process is simpler, but the minimum feature size that can be created is larger
Solution Approach 1:
The patent applies segmentation by dividing the single patterning step into multiple sequential patterning steps (double-patterning or multi-patterning). First, a mandrel pattern is formed, then spacers are deposited and patterned, followed by removal of the mandrel, and finally a second pattern is formed. This multi-stage approach enables creation of features at half the pitch of traditional single-step photolithography, directly resolving the contradiction between achieving smaller minimum feature size and maintaining fabrication process simplicity.
Solution Approach 2:
The patent employs preliminary action through the use of sacrificial mandrels and spacers that are formed in advance before the final pattern is created. The mandrels are formed first as temporary structures, then spacers are deposited around them, and only after these preliminary structures are in place is the final high-precision pattern achieved. This preliminary structuring enables the subsequent formation of smaller features while managing overall process complexity.
2Productivity
If feature sizes are reduced to increase functional density, then production efficiency improves and costs decrease, but processing and manufacturing difficulty increases
Solution Approach 1:
The patent applies self-service through self-aligned spacer formation where the spacer material automatically conforms to the mandrel structure during deposition, creating precisely positioned features without requiring additional alignment steps. The spacer width is determined by the deposition thickness rather than requiring separate lithography alignment, which simplifies the manufacturing process while enabling smaller feature sizes and increased functional density.
Solution Approach 2:
The patent utilizes parameter changes by controlling the thickness of deposited spacer layers to precisely define the final feature dimensions. By adjusting deposition parameters (thickness, uniformity, conformality), the process achieves smaller minimum feature sizes while maintaining manufacturing ease. The transition from lateral lithography limitations to vertical deposition control enables scaling to smaller dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable semiconductor devices with improved precision and reliability, enhancing processing efficiency and reducing manufacturing costs by allowing for smaller feature sizes and increased complexity in semiconductor design.
Implementation Method 1
The fin structure has multiple first sacrificial layers and multiple semiconductor layers laid out alternately. The semiconductor layers are formed by epitaxial growth.
Implementation Method 2
The first sacrificial layers are removed with an etchant to release multiple semiconductor nanostructures made of remaining portions of the semiconductor layers.
Data Source
AI summary
A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.


